525b311bf8
As usual these patches were extracted from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
36 lines
1.1 KiB
Diff
36 lines
1.1 KiB
Diff
From e3f14344d3d427d0b9cdbf4e3039d88320836471 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Mon, 15 Feb 2016 17:06:02 -0800
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Subject: [PATCH 291/304] drm/vc4: Fix the name of the VSYNCD_EVEN register.
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It's used for delaying vsync in interlaced mode.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit c31806fbdda910d337b60896040afa708bdfa2bd)
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
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drivers/gpu/drm/vc4/vc4_regs.h | 2 +-
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2 files changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -88,7 +88,7 @@ static const struct {
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} crtc_regs[] = {
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CRTC_REG(PV_CONTROL),
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CRTC_REG(PV_V_CONTROL),
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- CRTC_REG(PV_VSYNCD),
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+ CRTC_REG(PV_VSYNCD_EVEN),
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CRTC_REG(PV_HORZA),
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CRTC_REG(PV_HORZB),
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CRTC_REG(PV_VERTA),
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -187,7 +187,7 @@
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# define PV_VCONTROL_CONTINUOUS BIT(1)
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# define PV_VCONTROL_VIDEN BIT(0)
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-#define PV_VSYNCD 0x08
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+#define PV_VSYNCD_EVEN 0x08
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#define PV_HORZA 0x0c
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# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
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