8e49b4b902
This change set enables frequency scaling on ipq806x, which speeds-up the CPU and allows it to achieve its max frequency. These patches are cherry-picked & backported from the following location: *130-132: linux-next *133-143: LKML - https://lkml.org/lkml/2015/3/21/15 *144: derived from other qcom similar dts *145: derived from https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.14/drivers/cpufreq/cpufreq-krait.c Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45730
127 lines
3.3 KiB
Diff
127 lines
3.3 KiB
Diff
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
Subject: [v3,08/13] clk: qcom: Add IPQ806X's HFPLLs
|
|
From: Stephen Boyd <sboyd@codeaurora.org>
|
|
X-Patchwork-Id: 6063241
|
|
Message-Id: <1426920332-9340-9-git-send-email-sboyd@codeaurora.org>
|
|
To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
|
|
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
|
|
linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
|
|
Viresh Kumar <viresh.kumar@linaro.org>
|
|
Date: Fri, 20 Mar 2015 23:45:27 -0700
|
|
|
|
Describe the HFPLLs present on IPQ806X devices.
|
|
|
|
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
|
|
---
|
|
drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 83 insertions(+)
|
|
|
|
--- a/drivers/clk/qcom/gcc-ipq806x.c
|
|
+++ b/drivers/clk/qcom/gcc-ipq806x.c
|
|
@@ -30,6 +30,7 @@
|
|
#include "clk-pll.h"
|
|
#include "clk-rcg.h"
|
|
#include "clk-branch.h"
|
|
+#include "clk-hfpll.h"
|
|
#include "reset.h"
|
|
|
|
static struct clk_pll pll0 = {
|
|
@@ -102,6 +103,85 @@ static struct clk_regmap pll8_vote = {
|
|
},
|
|
};
|
|
|
|
+static struct hfpll_data hfpll0_data = {
|
|
+ .mode_reg = 0x3200,
|
|
+ .l_reg = 0x3208,
|
|
+ .m_reg = 0x320c,
|
|
+ .n_reg = 0x3210,
|
|
+ .config_reg = 0x3204,
|
|
+ .status_reg = 0x321c,
|
|
+ .config_val = 0x7845c665,
|
|
+ .droop_reg = 0x3214,
|
|
+ .droop_val = 0x0108c000,
|
|
+ .min_rate = 600000000UL,
|
|
+ .max_rate = 1800000000UL,
|
|
+};
|
|
+
|
|
+static struct clk_hfpll hfpll0 = {
|
|
+ .d = &hfpll0_data,
|
|
+ .clkr.hw.init = &(struct clk_init_data){
|
|
+ .parent_names = (const char *[]){ "pxo" },
|
|
+ .num_parents = 1,
|
|
+ .name = "hfpll0",
|
|
+ .ops = &clk_ops_hfpll,
|
|
+ .flags = CLK_IGNORE_UNUSED,
|
|
+ },
|
|
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
|
|
+};
|
|
+
|
|
+static struct hfpll_data hfpll1_data = {
|
|
+ .mode_reg = 0x3240,
|
|
+ .l_reg = 0x3248,
|
|
+ .m_reg = 0x324c,
|
|
+ .n_reg = 0x3250,
|
|
+ .config_reg = 0x3244,
|
|
+ .status_reg = 0x325c,
|
|
+ .config_val = 0x7845c665,
|
|
+ .droop_reg = 0x3314,
|
|
+ .droop_val = 0x0108c000,
|
|
+ .min_rate = 600000000UL,
|
|
+ .max_rate = 1800000000UL,
|
|
+};
|
|
+
|
|
+static struct clk_hfpll hfpll1 = {
|
|
+ .d = &hfpll1_data,
|
|
+ .clkr.hw.init = &(struct clk_init_data){
|
|
+ .parent_names = (const char *[]){ "pxo" },
|
|
+ .num_parents = 1,
|
|
+ .name = "hfpll1",
|
|
+ .ops = &clk_ops_hfpll,
|
|
+ .flags = CLK_IGNORE_UNUSED,
|
|
+ },
|
|
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
|
|
+};
|
|
+
|
|
+static struct hfpll_data hfpll_l2_data = {
|
|
+ .mode_reg = 0x3300,
|
|
+ .l_reg = 0x3308,
|
|
+ .m_reg = 0x330c,
|
|
+ .n_reg = 0x3310,
|
|
+ .config_reg = 0x3304,
|
|
+ .status_reg = 0x331c,
|
|
+ .config_val = 0x7845c665,
|
|
+ .droop_reg = 0x3314,
|
|
+ .droop_val = 0x0108c000,
|
|
+ .min_rate = 600000000UL,
|
|
+ .max_rate = 1800000000UL,
|
|
+};
|
|
+
|
|
+static struct clk_hfpll hfpll_l2 = {
|
|
+ .d = &hfpll_l2_data,
|
|
+ .clkr.hw.init = &(struct clk_init_data){
|
|
+ .parent_names = (const char *[]){ "pxo" },
|
|
+ .num_parents = 1,
|
|
+ .name = "hfpll_l2",
|
|
+ .ops = &clk_ops_hfpll,
|
|
+ .flags = CLK_IGNORE_UNUSED,
|
|
+ },
|
|
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
|
|
+};
|
|
+
|
|
+
|
|
static struct clk_pll pll14 = {
|
|
.l_reg = 0x31c4,
|
|
.m_reg = 0x31c8,
|
|
@@ -2261,6 +2341,9 @@ static struct clk_regmap *gcc_ipq806x_cl
|
|
[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
|
|
[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
|
|
[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
|
|
+ [PLL9] = &hfpll0.clkr,
|
|
+ [PLL10] = &hfpll1.clkr,
|
|
+ [PLL12] = &hfpll_l2.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
|