0cf32de17c
It's needed to support new devices that use specific pin functions. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
73 lines
1.6 KiB
Diff
73 lines
1.6 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 9 Nov 2018 09:53:56 +0100
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Subject: [PATCH] ARM: dts: BCM5301X: Describe Northstar pins mux controller
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This describes hardware & will allow referencing pin functions. The
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first usage is UART1 which allows supporting devices using it.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -37,6 +37,8 @@
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinmux_uart1>;
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status = "disabled";
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};
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};
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@@ -391,6 +393,48 @@
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status = "disabled";
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};
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+ dmu@1800c000 {
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+ compatible = "simple-bus";
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+ ranges = <0 0x1800c000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ cru@100 {
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+ compatible = "simple-bus";
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+ reg = <0x100 0x1a4>;
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+ ranges;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ pin-controller@1c0 {
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+ compatible = "brcm,bcm4708-pinmux";
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+ reg = <0x1c0 0x24>;
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+ reg-names = "cru_gpio_control";
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+
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+ spi-pins {
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+ groups = "spi_grp";
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+ function = "spi";
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+ };
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+
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+ i2c {
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+ groups = "i2c_grp";
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+ function = "i2c";
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+ };
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+
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+ pwm {
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+ groups = "pwm0_grp", "pwm1_grp",
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+ "pwm2_grp", "pwm3_grp";
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+ function = "pwm";
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+ };
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+
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+ pinmux_uart1: uart1 {
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+ groups = "uart1_grp";
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+ function = "uart1";
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+ };
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+ };
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+ };
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+ };
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+
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lcpll0: lcpll0@1800c100 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-lcpll0";
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