87 lines
3.2 KiB
C
87 lines
3.2 KiB
C
/*
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<:copyright-gpl
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Copyright 2004 Broadcom Corp. All Rights Reserved.
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This program is free software; you can distribute it and/or modify it
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under the terms of the GNU General Public License (Version 2) as
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published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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:>
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*/
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//
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// bcmpci.h - bcm96348 PCI, Cardbus, and PCMCIA definition
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//
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#ifndef BCMPCI_H
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#define BCMPCI_H
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/* Memory window in internal system bus address space */
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#define BCM_PCI_MEM_BASE 0x08000000
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/* IO window in internal system bus address space */
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#define BCM_PCI_IO_BASE 0x0C000000
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#define BCM_PCI_ADDR_MASK 0x1fffffff
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/* Memory window size (range) */
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#define BCM_PCI_MEM_SIZE_16MB 0x01000000
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/* IO window size (range) */
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#define BCM_PCI_IO_SIZE_64KB 0x00010000
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/* PCI Configuration and I/O space acesss */
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#define BCM_PCI_CFG(d, f, o) ( (d << 11) | (f << 8) | (o/4 << 2) )
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/* fake USB PCI slot */
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#define USB_HOST_SLOT 9
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#define USB_BAR0_MEM_SIZE 0x0800
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#define BCM_HOST_MEM_SPACE1 0x10000000
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#define BCM_HOST_MEM_SPACE2 0x00000000
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/*
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* EBI bus clock is 33MHz and share with PCI bus
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* each clock cycle is 30ns.
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*/
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/* attribute memory access wait cnt for 4306 */
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#define PCMCIA_ATTR_CE_HOLD 3 // data hold time 70ns
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#define PCMCIA_ATTR_CE_SETUP 3 // data setup time 50ns
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#define PCMCIA_ATTR_INACTIVE 6 // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4)
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#define PCMCIA_ATTR_ACTIVE 10 // OE/WE pulse width 300ns
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/* common memory access wait cnt for 4306 */
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#define PCMCIA_MEM_CE_HOLD 1 // data hold time 30ns
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#define PCMCIA_MEM_CE_SETUP 1 // data setup time 30ns
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#define PCMCIA_MEM_INACTIVE 2 // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4)
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#define PCMCIA_MEM_ACTIVE 5 // OE/WE pulse width 150ns
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#define PCCARD_VCC_MASK 0x00070000 // Mask Reset also
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#define PCCARD_VCC_33V 0x00010000
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#define PCCARD_VCC_50V 0x00020000
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typedef enum {
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MPI_CARDTYPE_NONE, // No Card in slot
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MPI_CARDTYPE_PCMCIA, // 16-bit PCMCIA card in slot
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MPI_CARDTYPE_CARDBUS, // 32-bit CardBus card in slot
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} CardType;
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#define CARDBUS_SLOT 0 // Slot 0 is default for CardBus
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#define pcmciaAttrOffset 0x00200000
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#define pcmciaMemOffset 0x00000000
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// Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA.
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#define pcmciaIoOffset (BCM_PCI_IO_BASE + 0x80000)
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// Base Address is that mapped into the MPI ChipSelect registers.
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// UBUS bridge MemoryWindow 0 outputs a 0x00 for the base.
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#define pcmciaBase 0xbf000000
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#define pcmciaAttr (pcmciaAttrOffset | pcmciaBase)
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#define pcmciaMem (pcmciaMemOffset | pcmciaBase)
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#define pcmciaIo (pcmciaIoOffset | pcmciaBase)
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#endif
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