8fdda1cc10
This patch is to add linux 4.9 support for layerscape. All these kernel patches are from NXP LSDK 1709 release. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
149 lines
4.8 KiB
Diff
149 lines
4.8 KiB
Diff
From 505eb62bdb7a4cc25b13491dd5c68d0741c5d6da Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Mon, 25 Sep 2017 12:21:13 +0800
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Subject: [PATCH] ata: support layerscape
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This is a integrated patch for layerscape sata support.
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Signed-off-by: Tang Yuantian <Yuantian.Tang@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/ata/ahci_qoriq.c | 63 ++++++++++++++++++++++++++++++++++++++++++------
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1 file changed, 56 insertions(+), 7 deletions(-)
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diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
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index 1eba8dff..2f30a39f 100644
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--- a/drivers/ata/ahci_qoriq.c
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+++ b/drivers/ata/ahci_qoriq.c
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@@ -1,7 +1,7 @@
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/*
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* Freescale QorIQ AHCI SATA platform driver
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*
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- * Copyright 2015 Freescale, Inc.
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+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
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* Tang Yuantian <Yuantian.Tang@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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@@ -46,23 +46,32 @@
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#define LS1021A_AXICC_ADDR 0xC0
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#define SATA_ECC_DISABLE 0x00020000
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+#define ECC_DIS_ARMV8_CH2 0x80000000
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+#define ECC_DIS_LS1088A 0x40000000
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enum ahci_qoriq_type {
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AHCI_LS1021A,
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AHCI_LS1043A,
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AHCI_LS2080A,
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+ AHCI_LS1046A,
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+ AHCI_LS1088A,
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+ AHCI_LS2088A,
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};
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struct ahci_qoriq_priv {
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struct ccsr_ahci *reg_base;
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enum ahci_qoriq_type type;
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void __iomem *ecc_addr;
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+ bool is_dmacoherent;
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};
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static const struct of_device_id ahci_qoriq_of_match[] = {
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{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
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{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
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{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
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+ { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
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+ { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
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+ { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
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{},
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};
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MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
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@@ -154,6 +163,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
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switch (qpriv->type) {
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case AHCI_LS1021A:
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+ if (!qpriv->ecc_addr)
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+ return -EINVAL;
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writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
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@@ -161,19 +172,56 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
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writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
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writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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- writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
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+ if (qpriv->is_dmacoherent)
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+ writel(AHCI_PORT_AXICC_CFG,
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+ reg_base + LS1021A_AXICC_ADDR);
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break;
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case AHCI_LS1043A:
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+ if (!qpriv->ecc_addr)
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+ return -EINVAL;
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+ writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
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+ qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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+ if (qpriv->is_dmacoherent)
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+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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case AHCI_LS2080A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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+ if (qpriv->is_dmacoherent)
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+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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+ break;
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+
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+ case AHCI_LS1046A:
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+ if (!qpriv->ecc_addr)
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+ return -EINVAL;
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+ writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
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+ qpriv->ecc_addr);
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+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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+ if (qpriv->is_dmacoherent)
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+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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+ break;
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+
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+ case AHCI_LS1088A:
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+ if (!qpriv->ecc_addr)
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+ return -EINVAL;
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+ writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
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+ qpriv->ecc_addr);
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+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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+ if (qpriv->is_dmacoherent)
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+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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+ break;
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+
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+ case AHCI_LS2088A:
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+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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+ if (qpriv->is_dmacoherent)
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+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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}
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@@ -204,13 +252,14 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
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qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
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- if (qoriq_priv->type == AHCI_LS1021A) {
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- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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- "sata-ecc");
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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+ "sata-ecc");
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+ if (res) {
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qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
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if (IS_ERR(qoriq_priv->ecc_addr))
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return PTR_ERR(qoriq_priv->ecc_addr);
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}
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+ qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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--
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2.14.1
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