145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
/*
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* HND SiliconBackplane Gigabit Ethernet core software interface
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#include <typedefs.h>
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#include <osl.h>
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#include <pcicfg.h>
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#include <sbconfig.h>
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#include <sbutils.h>
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#include "sbgige.h"
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#include <hndpci.h>
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#include "hndgige.h"
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uint32
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sb_base(uint32 admatch)
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{
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uint32 base;
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uint type;
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type = admatch & SBAM_TYPE_MASK;
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ASSERT(type < 3);
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base = 0;
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if (type == 0) {
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base = admatch & SBAM_BASE0_MASK;
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} else if (type == 1) {
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ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
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base = admatch & SBAM_BASE1_MASK;
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} else if (type == 2) {
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ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
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base = admatch & SBAM_BASE2_MASK;
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}
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return (base);
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}
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/*
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* Setup the gige core.
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* Resetting the core will lose all settings.
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*/
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void
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sb_gige_init(sb_t *sbh, uint32 unit, bool *rgmii)
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{
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volatile pci_config_regs *pci;
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sbgige_pcishim_t *ocp;
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sbconfig_t *sb;
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osl_t *osh;
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uint32 statelow;
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uint32 statehigh;
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uint32 base;
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uint32 idx;
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void *regs;
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/* Sanity checks */
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ASSERT(sbh);
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ASSERT(rgmii);
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idx = sb_coreidx(sbh);
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/* point to the gige core registers */
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regs = sb_setcore(sbh, SB_GIGETH, unit);
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ASSERT(regs);
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osh = sb_osh(sbh);
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pci = &((sbgige_t *)regs)->pcicfg;
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ocp = &((sbgige_t *)regs)->pcishim;
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sb = &((sbgige_t *)regs)->sbconfig;
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/* Enable the core clock and memory access */
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if (!sb_iscoreup(sbh))
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sb_core_reset(sbh, 0, 0);
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/*
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* Setup the 64K memory-mapped region base address through BAR0.
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* Leave the other BAR values alone.
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*/
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base = sb_base(R_REG(osh, &sb->sbadmatch1));
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W_REG(osh, &pci->base[0], base);
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W_REG(osh, &pci->base[1], 0);
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/*
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* Enable the PCI memory access anyway. Any PCI config commands
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* issued before the core is enabled will go to the emulation
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* only and will not go to the real PCI config registers.
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*/
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OR_REG(osh, &pci->command, 2);
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/*
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* Enable the posted write flush scheme as follows:
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*
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* - Enable flush on any core register read
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* - Enable timeout on the flush
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* - Disable the interrupt mask when flushing
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*
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* This differs from the default setting only in that interrupts are
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* not masked. Since posted writes are not flushed on interrupt, the
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* driver must explicitly request a flush in its interrupt handling
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* by reading a core register.
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*/
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W_REG(osh, &ocp->FlushStatusControl, 0x68);
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/*
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* Determine whether the GbE is in GMII or RGMII mode. This is
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* indicated in bit 16 of the SBTMStateHigh register, which is
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* part of the core-specific flags field.
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*
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* For GMII, bypass the Rx/Tx DLLs, i.e. add no delay to RXC/GTXC
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* within the core. For RGMII, do not bypass the DLLs, resulting
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* in added delay for RXC/GTXC. The SBTMStateLow register contains
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* the controls for doing this in the core-specific flags field:
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*
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* bit 24 - Enable DLL controls
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* bit 20 - Bypass Rx DLL
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* bit 19 - Bypass Tx DLL
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*/
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statelow = R_REG(osh, &sb->sbtmstatelow); /* DLL controls */
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statehigh = R_REG(osh, &sb->sbtmstatehigh); /* GMII/RGMII mode */
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if ((statehigh & (1 << 16)) != 0) /* RGMII */
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{
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statelow &= ~(1 << 20); /* no Rx bypass (delay) */
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statelow &= ~(1 << 19); /* no Tx bypass (delay) */
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*rgmii = TRUE;
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}
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else /* GMII */
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{
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statelow |= (1 << 20); /* Rx bypass (no delay) */
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statelow |= (1 << 19); /* Tx bypass (no delay) */
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*rgmii = FALSE;
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}
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statelow |= (1 << 24); /* enable DLL controls */
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W_REG(osh, &sb->sbtmstatelow, statelow);
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sb_setcoreidx(sbh, idx);
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}
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