38 lines
1.5 KiB
Diff
38 lines
1.5 KiB
Diff
From: Paul Burton <paul.burton@imgtec.com>
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Date: Mon, 5 Sep 2016 15:24:54 +0100
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Subject: [PATCH] MIPS: c-r4k: Fix size calc when avoiding IPIs for small
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icache flushes
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Commit f70ddc07b637 ("MIPS: c-r4k: Avoid small flush_icache_range SMP
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calls") adds checks to force use of hit-type cache ops for small icache
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flushes where they are globalised & index-type cache ops aren't, in
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order to avoid the overhead of IPIs in those cases. However it
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calculated the size of the region being flushed incorrectly, subtracting
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the end address from the start address rather than the reverse. This
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would have led to an overflow with size wrapping round to some large
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value, and likely to the special case for avoiding IPIs not actually
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being hit.
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Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Cc: James Hogan <james.hogan@imgtec.com>
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Fixes: f70ddc07b637 ("MIPS: c-r4k: Avoid small flush_icache_range SMP calls")
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Reviewed-by: James Hogan <james.hogan@imgtec.com>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Cc: Huacai Chen <chenhc@lemote.com>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/14211/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -781,7 +781,7 @@ static void r4k_flush_icache_range(unsig
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* If address-based cache ops are globalized, then we may be
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* able to avoid the IPI for small flushes.
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*/
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- size = start - end;
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+ size = end - start;
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cache_size = icache_size;
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if (!cpu_has_ic_fills_f_dc) {
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size *= 2;
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