f67b0276b6
This commit adds 4 patches, one per kernel version that was used for picking updates. This adds support for few new PHYs. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
136 lines
4.7 KiB
Diff
136 lines
4.7 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Subject: [PATCH 2/2] net: phy: pick Broadcom drivers updates from net-next for
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4.11
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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--- a/drivers/net/phy/bcm7xxx.c
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+++ b/drivers/net/phy/bcm7xxx.c
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@@ -163,12 +163,43 @@ static int bcm7xxx_28nm_e0_plus_afe_conf
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return 0;
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}
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+static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
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+{
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+ /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
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+ bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
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+
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+ /* Cut master bias current by 2% to compensate for RC_CAL offset */
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+ bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
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+
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+ /* Improve hybrid leakage */
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+ bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
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+
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+ /* Change rx_on_tune 8 to 0xf */
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+ bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
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+
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+ /* Change 100Tx EEE bandwidth */
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+ bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
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+
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+ /* Enable ffe zero detection for Vitesse interoperability */
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+ bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
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+
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+ r_rc_cal_reset(phydev);
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+
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+ return 0;
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+}
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+
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static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
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{
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u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
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u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
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int ret = 0;
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+ /* Newer devices have moved the revision information back into a
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+ * standard location in MII_PHYS_ID[23]
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+ */
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+ if (rev == 0)
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+ rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
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+
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pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
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dev_name(&phydev->dev), phydev->drv->name, rev, patch);
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@@ -192,6 +223,9 @@ static int bcm7xxx_28nm_config_init(stru
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case 0x10:
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ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
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break;
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+ case 0x01:
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+ ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
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+ break;
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default:
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break;
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}
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@@ -336,6 +370,7 @@ static int bcm7xxx_suspend(struct phy_de
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static struct phy_driver bcm7xxx_driver[] = {
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
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+ BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
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@@ -350,6 +385,7 @@ static struct phy_driver bcm7xxx_driver[
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static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
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{ PHY_ID_BCM7250, 0xfffffff0, },
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+ { PHY_ID_BCM7278, 0xfffffff0, },
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{ PHY_ID_BCM7364, 0xfffffff0, },
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{ PHY_ID_BCM7366, 0xfffffff0, },
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{ PHY_ID_BCM7346, 0xfffffff0, },
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--- a/drivers/net/phy/broadcom.c
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+++ b/drivers/net/phy/broadcom.c
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@@ -395,12 +395,10 @@ static int bcm54612e_config_aneg(struct
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(phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
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u16 reg;
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- /* Errata: reads require filling in the write selector field */
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- bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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- MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
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- reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
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+ reg = bcm54xx_auxctl_read(phydev,
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+ MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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/* Disable RXD to RXC delay (default set) */
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- reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
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+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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/* Clear shadow selector field */
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reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
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bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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--- a/include/linux/brcmphy.h
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+++ b/include/linux/brcmphy.h
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@@ -24,6 +24,7 @@
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#define PHY_ID_BCM57780 0x03625d90
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#define PHY_ID_BCM7250 0xae025280
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+#define PHY_ID_BCM7278 0xae0251a0
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#define PHY_ID_BCM7364 0xae025260
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#define PHY_ID_BCM7366 0x600d8490
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#define PHY_ID_BCM7346 0x600d8650
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@@ -103,18 +104,17 @@
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/*
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* AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
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*/
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-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
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#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
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#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
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-#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
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-#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
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-#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
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-#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
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-#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
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-#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
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-#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
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+#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
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+#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
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#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
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/*
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