559 lines
18 KiB
Diff
559 lines
18 KiB
Diff
--- a/src/drv_vmmc_access.h
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+++ b/src/drv_vmmc_access.h
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@@ -24,6 +24,10 @@
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#include "drv_mps_vmmc.h"
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#endif
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+# define IFX_MPS IFXMIPS_MPS_BASE_ADDR
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+#endif
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+
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/* ============================= */
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/* Global Defines */
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/* ============================= */
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--- a/src/drv_vmmc_bbd.c
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+++ b/src/drv_vmmc_bbd.c
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@@ -1072,7 +1072,11 @@
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IFX_uint8_t padBytes = 0;
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#endif
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IFX_uint16_t cram_offset, cram_crc,
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- pCmd [MAX_CMD_WORD] = {0};
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+ pCmd [MAX_CMD_WORD]
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+#if defined (__GNUC__) || defined (__GNUG__)
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+ __attribute__ ((aligned(4)))
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+#endif
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+ = {0};
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/* read offset */
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cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t));
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--- a/src/drv_vmmc_danube.h
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+++ b/src/drv_vmmc_danube.h
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@@ -15,56 +15,18 @@
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*/
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#if defined SYSTEM_DANUBE
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-#include <asm/ifx/ifx_gpio.h>
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+#include <xway/xway.h>
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+
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#else
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#error no system selected
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#endif
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-#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC
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+#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC
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/**
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*/
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#define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
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do { \
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- ret = VMMC_statusOk; \
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- /* Reserve P0.0 as TDM/FSC */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
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- \
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- /* Reserve P1.9 as TDM/DO */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- \
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- /* Reserve P1.10 as TDM/DI */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\
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- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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- \
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- /* Reserve P1.11 as TDM/DCL */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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- \
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- if (mode == 2) { \
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- /* TDM/FSC+DCL Master */ \
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- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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- } else { \
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- /* TDM/FSC+DCL Slave */ \
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- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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- } \
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} while(0);
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/**
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@@ -72,11 +34,6 @@
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*/
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#define VMMC_DRIVER_UNLOAD_HOOK(ret) \
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do { \
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- ret = VMMC_statusOk; \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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} while (0)
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#endif /* _DRV_VMMC_AMAZON_S_H */
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--- a/src/drv_vmmc_init.c
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+++ b/src/drv_vmmc_init.c
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@@ -52,6 +52,14 @@
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#include "ifx_pmu.h"
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#endif /* PMU_SUPPORTED */
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
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+# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
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+# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
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+# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
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+# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
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+# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
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+#endif
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/* ============================= */
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/* Local Macros & Definitions */
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--- a/src/drv_vmmc_init_cap.c
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+++ b/src/drv_vmmc_init_cap.c
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@@ -22,6 +22,11 @@
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#include "drv_mps_vmmc.h"
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#include "drv_mps_vmmc_device.h"
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+# define IFX_MPS_CHIPID_VERSION_GET IFXMIPS_MPS_CHIPID_VERSION_GET
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+# define IFX_MPS_CHIPID IFXMIPS_MPS_CHIPID
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+#endif
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+
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/* ============================= */
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/* Configuration defintions */
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/* ============================= */
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--- a/src/mps/drv_mps_vmmc_common.c
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+++ b/src/mps/drv_mps_vmmc_common.c
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@@ -17,6 +17,7 @@
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/* Includes */
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/* ============================= */
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#include "drv_config.h"
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+#include "drv_vmmc_init.h"
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#undef USE_PLAIN_VOICE_FIRMWARE
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#undef PRINT_ON_ERR_INTERRUPT
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@@ -35,8 +36,35 @@
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#include "ifxos_interrupt.h"
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#include "ifxos_time.h"
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx/ifx_gptu.h>
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+# include <lantiq.h>
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+# include <irq.h>
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+# include <lantiq_timer.h>
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+
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+# define ifx_gptu_timer_request lq_request_timer
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+# define ifx_gptu_timer_start lq_start_timer
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+# define ifx_gptu_countvalue_get lq_get_count_value
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+# define ifx_gptu_timer_free lq_free_timer
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+
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+# define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
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+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
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+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
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+# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
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+# define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR
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+# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
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+# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
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+# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
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+# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
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+# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
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+# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
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+
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+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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+
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+# define bsp_mask_and_ack_irq lq_mask_and_ack_irq
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+#else
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+# include <asm/ifx/ifx_regs.h>
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+# include <asm/ifx/ifx_gptu.h>
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+#endif
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#include "drv_mps_vmmc.h"
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#include "drv_mps_vmmc_dbg.h"
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@@ -201,7 +229,8 @@
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*/
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IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
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{
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- IFX_uint32_t ptr, flags;
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+ unsigned long flags;
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+ IFX_uint32_t ptr;
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IFX_int32_t index = fastbuf_index;
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if (fastbuf_initialized == 0)
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@@ -255,7 +284,7 @@
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*/
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IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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IFX_int32_t index = fastbuf_index;
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IFXOS_LOCKINT (flags);
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@@ -451,7 +480,7 @@
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*/
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static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
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{
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@@ -478,7 +507,7 @@
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*/
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static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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if (mps_buffer.buf_level < value)
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{
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@@ -946,7 +975,7 @@
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mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
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IFX_boolean_t from_kernel)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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IFXOS_LOCKINT (flags);
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@@ -1062,7 +1091,7 @@
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IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
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{
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IFX_int32_t count;
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- IFX_uint32_t flags;
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+ unsigned long flags;
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IFXOS_LOCKINT (flags);
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IFXOS_BlockFree (pFW_img_data);
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@@ -1558,7 +1587,7 @@
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IFX_uint32_t * bytes)
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{
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IFX_int32_t i, ret;
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- IFX_uint32_t flags;
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+ unsigned long flags;
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IFXOS_LOCKINT (flags);
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@@ -1768,7 +1797,7 @@
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{
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mps_fifo *mbx;
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IFX_uint32_t i;
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- IFX_uint32_t flags;
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+ unsigned long flags;
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IFX_int32_t retval = -EAGAIN;
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IFX_int32_t retries = 0;
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IFX_uint32_t word = 0;
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@@ -2163,6 +2192,7 @@
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TRACE (MPS, DBG_LEVEL_HIGH,
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("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
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}
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+
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return retval;
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}
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@@ -2186,7 +2216,7 @@
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mps_mbx_dev *mbx_dev;
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MbxMsg_s msg;
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IFX_uint32_t bytes_read = 0;
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- IFX_uint32_t flags;
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+ unsigned long flags;
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IFX_int32_t ret;
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/* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
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@@ -2277,7 +2307,7 @@
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{
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ifx_mps_bufman_dec_level (1);
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if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
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- (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
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+ ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
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{
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IFXOS_LockRelease (pMPSDev->provide_buffer);
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}
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@@ -2320,7 +2350,7 @@
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#endif /* CONFIG_PROC_FS */
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ifx_mps_bufman_dec_level (1);
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if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
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- (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
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+ ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
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{
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IFXOS_LockRelease (pMPSDev->provide_buffer);
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}
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@@ -2350,7 +2380,7 @@
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IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
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{
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mps_fifo *mbx;
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- IFX_uint32_t flags;
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+ unsigned long flags;
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/* set pointer to upstream command mailbox */
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mbx = &(pMPSDev->cmd_upstrm_fifo);
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@@ -2398,7 +2428,7 @@
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mps_event_msg msg;
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IFX_int32_t length = 0;
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IFX_int32_t read_length = 0;
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- IFX_uint32_t flags;
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+ unsigned long flags;
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/* set pointer to upstream event mailbox */
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mbx = &(pMPSDev->event_upstrm_fifo);
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@@ -2641,7 +2671,7 @@
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*/
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IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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MPS_Ad0Reg_u Ad0Reg;
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IFXOS_LOCKINT (flags);
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@@ -2667,7 +2697,7 @@
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*/
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IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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MPS_Ad0Reg_u Ad0Reg;
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IFXOS_LOCKINT (flags);
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@@ -2794,6 +2824,7 @@
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}
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}
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+
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if (MPS_Ad0StatusReg.fld.du_mbx)
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{
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#ifdef CONFIG_PROC_FS
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@@ -3087,7 +3118,8 @@
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*/
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IFX_return_t ifx_mps_init_gpt ()
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{
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- IFX_uint32_t flags, timer_flags, timer, loops = 0;
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+ unsigned long flags;
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+ IFX_uint32_t timer_flags, timer, loops = 0;
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IFX_ulong_t count;
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#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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timer = TIMER1A;
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--- a/src/mps/drv_mps_vmmc_danube.c
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+++ b/src/mps/drv_mps_vmmc_danube.c
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@@ -32,9 +32,21 @@
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#include "ifxos_select.h"
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#include "ifxos_interrupt.h"
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx/ifx_gpio.h>
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-#include <asm/ifx/common_routines.h>
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+# include <lantiq.h>
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+# include <irq.h>
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+# include <lantiq_timer.h>
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+# include <linux/dma-mapping.h>
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+
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+
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+# define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
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+#define IFX_RCU_RST_REQ_CPU1 (1 << 3)
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+# define IFX_RCU_RST_REQ LQ_RCU_RST
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+#else
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+# include <asm/ifx/ifx_regs.h>
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+# include <asm/ifx_vpe.h>
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+# include <asm/ifx/ifx_gpio.h>
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+#endif
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#include "drv_mps_vmmc.h"
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#include "drv_mps_vmmc_dbg.h"
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@@ -71,6 +83,20 @@
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/* Local function definition */
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/* ============================= */
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+IFX_uint32_t ifx_get_cp1_size(IFX_void_t)
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+{
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+ return 2;
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+}
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+
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+unsigned int *lq_get_cp1_base(void);
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+
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+IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)
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+{
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+ return lq_get_cp1_base();
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+}
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+#endif
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+
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/******************************************************************************
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* DANUBE Specific Routines
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******************************************************************************/
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@@ -130,6 +156,15 @@
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}
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/* check if FW image fits in available memory space */
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+ if (mem > ifx_get_cp1_size()<<20)
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+ {
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+ TRACE (MPS, DBG_LEVEL_HIGH,
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+ ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
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+ __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));
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+ return IFX_ERROR;
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+ }
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+#else
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if (mem > ifx_get_cp1_size())
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{
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TRACE (MPS, DBG_LEVEL_HIGH,
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@@ -137,6 +172,7 @@
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__FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
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return IFX_ERROR;
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}
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+#endif
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/* reset the driver */
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ifx_mps_reset ();
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@@ -357,7 +393,7 @@
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*/
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IFX_void_t ifx_mps_wdog_expiry()
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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|
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IFXOS_LOCKINT (flags);
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/* recalculate and compare the firmware checksum */
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--- a/src/mps/drv_mps_vmmc_device.h
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+++ b/src/mps/drv_mps_vmmc_device.h
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@@ -16,8 +16,15 @@
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declarations.
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*******************************************************************************/
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx_vpe.h>
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+# include <lantiq.h>
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+# include <irq.h>
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+# include <xway/xway.h>
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+# include <gpio.h>
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+#else
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+# include <asm/ifx/ifx_regs.h>
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+# include <asm/ifx_vpe.h>
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+#endif
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/* ============================= */
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/* MPS Common defines */
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--- a/src/mps/drv_mps_vmmc_linux.c
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+++ b/src/mps/drv_mps_vmmc_linux.c
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@@ -40,10 +40,28 @@
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#include <linux/moduleparam.h>
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#endif /* */
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|
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-
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-#include <asm/ifx/irq.h>
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx_vpe.h>
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+#include "drv_vmmc_init.h"
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+# include <lantiq.h>
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+# include <irq.h>
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+
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+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
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+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
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+# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
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+# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
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+# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
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+# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
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+
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|
+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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+# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
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|
+# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
|
|
+#define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
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+# define IFX_ICU_IM4_IER (LQ_ICU_BASE_ADDR + 0x00A8)
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|
+#else
|
|
+# include <asm/ifx/irq.h>
|
|
+# include <asm/ifx/ifx_regs.h>
|
|
+# include <asm/ifx_vpe.h>
|
|
+#endif
|
|
|
|
/* lib_ifxos headers */
|
|
#include "ifx_types.h"
|
|
@@ -915,7 +933,7 @@
|
|
#endif /* MPS_FIFO_BLOCKING_WRITE */
|
|
case FIO_MPS_GET_STATUS:
|
|
{
|
|
- IFX_uint32_t flags;
|
|
+ unsigned long flags;
|
|
|
|
/* get the status of the channel */
|
|
if (!from_kernel)
|
|
@@ -949,7 +967,7 @@
|
|
#if CONFIG_MPS_HISTORY_SIZE > 0
|
|
case FIO_MPS_GET_CMD_HISTORY:
|
|
{
|
|
- IFX_uint32_t flags;
|
|
+ unsigned long flags;
|
|
|
|
if (from_kernel)
|
|
{
|
|
@@ -1641,6 +1659,7 @@
|
|
sprintf (buf + len, " minLv: \t %8d\n",
|
|
ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
|
|
}
|
|
+
|
|
return len;
|
|
}
|
|
|
|
--- a/src/drv_vmmc_init.h
|
|
+++ b/src/drv_vmmc_init.h
|
|
@@ -53,4 +53,41 @@
|
|
extern IFX_int32_t VMMC_DeviceDriverStart(IFX_void_t);
|
|
extern IFX_void_t VMMC_DeviceDriverStop(IFX_void_t);
|
|
|
|
+
|
|
+#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
|
|
+#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
|
|
+
|
|
+#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
|
|
+#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
|
|
+#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
|
|
+#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
|
|
+#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
|
|
+#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
|
|
+#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
|
|
+#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
|
|
+#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
|
|
+#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
|
|
+#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
|
|
+#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
|
|
+#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
|
|
+#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
|
|
+#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
|
|
+#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
|
|
+#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
|
|
+#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
|
|
+#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
|
|
+#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
|
|
+#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
|
|
+#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
|
|
+#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
|
|
+#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
|
|
+#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
|
|
+
|
|
+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
|
|
+#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28)
|
|
+#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
|
|
+#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)
|
|
+#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
|
|
+#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)
|
|
+
|
|
#endif /* _DRV_VMMC_INIT_H */
|
|
--- a/src/drv_vmmc_ioctl.c
|
|
+++ b/src/drv_vmmc_ioctl.c
|
|
@@ -18,6 +18,7 @@
|
|
/* Includes */
|
|
/* ============================= */
|
|
#include "drv_api.h"
|
|
+#include "drv_vmmc_init.h"
|
|
#include "drv_vmmc_api.h"
|
|
#include "drv_vmmc_bbd.h"
|
|
|