5d52f4b51d
This change adds DWC3 QCOM USB phys and TCSR drivers. These are cherry-picked from the following LKML threads: *dwc3 qcom: https://lkml.org/lkml/2014/9/12/599 *tcsr: https://lkml.org/lkml/2015/2/9/579 We're also adding an additional patch to add the corresponding dev nodes in the IPQ806x and AP148 dts files. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45261
125 lines
2.4 KiB
Diff
125 lines
2.4 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
|
@@ -112,5 +112,29 @@
|
|
sata@29000000 {
|
|
status = "ok";
|
|
};
|
|
+
|
|
+ phy@100f8800 { /* USB3 port 1 HS phy */
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ phy@100f8830 { /* USB3 port 1 SS phy */
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ phy@110f8800 { /* USB3 port 0 HS phy */
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ phy@110f8830 { /* USB3 port 0 SS phy */
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ usb30@0 {
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ usb30@1 {
|
|
+ status = "ok";
|
|
+ };
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
@@ -291,5 +291,90 @@
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
+
|
|
+ hs_phy_1: phy@100f8800 {
|
|
+ compatible = "qcom,dwc3-hs-usb-phy";
|
|
+ reg = <0x100f8800 0x30>;
|
|
+ clocks = <&gcc USB30_1_UTMI_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ss_phy_1: phy@100f8830 {
|
|
+ compatible = "qcom,dwc3-ss-usb-phy";
|
|
+ reg = <0x100f8830 0x30>;
|
|
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hs_phy_0: phy@110f8800 {
|
|
+ compatible = "qcom,dwc3-hs-usb-phy";
|
|
+ reg = <0x110f8800 0x30>;
|
|
+ clocks = <&gcc USB30_0_UTMI_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ss_phy_0: phy@110f8830 {
|
|
+ compatible = "qcom,dwc3-ss-usb-phy";
|
|
+ reg = <0x110f8830 0x30>;
|
|
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb3_0: usb30@0 {
|
|
+ compatible = "qcom,dwc3";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+
|
|
+ ranges;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@11000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x11000000 0xcd00>;
|
|
+ interrupts = <0 110 0x4>;
|
|
+ phys = <&hs_phy_0>, <&ss_phy_0>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ tx-fifo-resize;
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb3_1: usb30@1 {
|
|
+ compatible = "qcom,dwc3";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+
|
|
+ ranges;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@10000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x10000000 0xcd00>;
|
|
+ interrupts = <0 205 0x4>;
|
|
+ phys = <&hs_phy_1>, <&ss_phy_1>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ tx-fifo-resize;
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
+
|
|
};
|
|
};
|