d8655868ca
Upstream handling of MIPS CPU IRQs is rather hackish and the interrupts are being enabled unconditionally in various places because of legacy code. Performance counter events are routed both through the GIC and through legacy CPU IRQ7 events, causing spurious interrupts. Fix this by disabling IRQ7 when trying to access the performance counter IRQ. Signed-off-by: Felix Fietkau <nbd@nbd.name>
15 lines
355 B
Diff
15 lines
355 B
Diff
--- a/arch/mips/ralink/irq-gic.c
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+++ b/arch/mips/ralink/irq-gic.c
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@@ -15,6 +15,12 @@
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int get_c0_perfcount_int(void)
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{
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+ /*
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+ * Performance counter events are routed through GIC.
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+ * Prevent them from firing on CPU IRQ7 as well
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+ */
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+ clear_c0_status(IE_SW0 << 7);
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+
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return gic_get_c0_perfcount_int();
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}
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EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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