65 lines
1.7 KiB
Diff
65 lines
1.7 KiB
Diff
--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -13,6 +13,22 @@
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#include <asm/smtc_ipi.h>
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#include <asm/time.h>
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+/*
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+ * Compare interrupt can be routed and latched outside the core,
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+ * so a single execution hazard barrier may not be enough to give
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+ * it time to clear as seen in the Cause register. 4 time the
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+ * pipeline depth seems reasonably conservative, and empirically
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+ * works better in configurations with high CPU/bus clock ratios.
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+ */
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+
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+#define compare_change_hazard() \
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+ do { \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ } while (0)
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+
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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@@ -28,6 +44,7 @@
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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+ compare_change_hazard();
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res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
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#ifdef CONFIG_MIPS_MT_SMTC
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evpe(vpflags);
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@@ -187,7 +204,7 @@
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*/
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if (c0_compare_int_pending()) {
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write_c0_compare(read_c0_count());
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- irq_disable_hazard();
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+ compare_change_hazard();
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if (c0_compare_int_pending())
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return 0;
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}
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@@ -196,7 +213,7 @@
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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- irq_disable_hazard();
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+ compare_change_hazard();
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if ((int)(read_c0_count() - cnt) < 0)
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break;
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/* increase delta if the timer was already expired */
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@@ -205,11 +222,12 @@
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while ((int)(read_c0_count() - cnt) <= 0)
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; /* Wait for expiry */
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+ compare_change_hazard();
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if (!c0_compare_int_pending())
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return 0;
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write_c0_compare(read_c0_count());
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- irq_disable_hazard();
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+ compare_change_hazard();
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if (c0_compare_int_pending())
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return 0;
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