97 lines
2.9 KiB
Diff
97 lines
2.9 KiB
Diff
From 6efc8d9081b70dcf71d7e8efd7b51d48ee2541be Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 2 Mar 2016 07:18:52 +0100
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Subject: [PATCH 048/102] net-next: mediatek: document MediaTek SoC ethernet
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binding
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This adds the binding documentation for the MediaTek Ethernet
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controller.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Rob Herring <robh@kernel.org>
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Cc: devicetree@vger.kernel.org
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---
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.../devicetree/bindings/net/mediatek-net.txt | 77 ++++++++++++++++++++
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1 file changed, 77 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
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@@ -0,0 +1,77 @@
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+MediaTek Frame Engine Ethernet controller
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+=========================================
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+
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+The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
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+have dual GMAC each represented by a child node..
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+
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+* Ethernet controller node
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+
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+Required properties:
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+- compatible: Should be "mediatek,mt7623-eth"
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+- reg: Address and length of the register set for the device
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+- interrupts: Should contain the frame engines interrupt
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+- clocks: the clock used by the core
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+- clock-names: the names of the clock listed in the clocks property. These are
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+ "ethif", "esw", "gp2", "gp1"
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+- power-domains: phandle to the power domain that the ethernet is part of
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+- resets: Should contain a phandle to the ethsys reset signal
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+- reset-names: Should contain the reset signal name "eth"
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+- mediatek,ethsys: phandle to the syscon node that handles the port setup
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+- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
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+ and driver current
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+
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+Optional properties:
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+- interrupt-parent: Should be the phandle for the interrupt controller
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+ that services interrupts for this device
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+
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+
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+* Ethernet MAC node
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+
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+Required properties:
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+- compatible: Should be "mediatek,eth-mac"
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+- reg: The number of the MAC
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+- phy-handle: see ethernet.txt file in the same directory.
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+
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+Example:
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+
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+eth: ethernet@1b100000 {
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+ compatible = "mediatek,mt7623-eth";
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+ reg = <0 0x1b100000 0 0x20000>;
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+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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+ <ðsys CLK_ETHSYS_ESW>,
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+ <ðsys CLK_ETHSYS_GP2>,
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+ <ðsys CLK_ETHSYS_GP1>;
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+ clock-names = "ethif", "esw", "gp2", "gp1";
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+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
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+ resets = <ðsys MT2701_ETHSYS_ETH_RST>;
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+ reset-names = "eth";
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+ mediatek,ethsys = <ðsys>;
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+ mediatek,pctl = <&syscfg_pctl_a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gmac1: mac@0 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <0>;
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+ phy-handle = <&phy0>;
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+ };
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+
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+ gmac2: mac@1 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <1>;
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+ phy-handle = <&phy1>;
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+ };
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+
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+ mdio-bus {
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+ phy0: ethernet-phy@0 {
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+ reg = <0>;
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+ phy-mode = "rgmii";
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+ };
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+
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+ phy1: ethernet-phy@1 {
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+ reg = <1>;
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+ phy-mode = "rgmii";
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+ };
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+ };
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+};
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