36a96a4493
In current state there's huge regression on ipq806x target that causes the device to transmit broken/malformed frames that are not corrected/detected by error control mechanisms and other less severe issues. https://bugs.lede-project.org/index.php?do=details&task_id=1197 This finally had been narrowed down to patch 0071-pcie-qcom-fixes.patch Meanwhile QSDK contains a handful of commits that add support for ipq806x to upstream qcom pcie driver https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/log/drivers/pci/host/pcie-qcom.c?h=eggplant Unfortunately qca developers do not bother to push it upstream. Using those commits instead of lede 0071 patch fixes mentioned issue and probably many others as it seems that corrupted data has been originating within pcie misconfiguration. Fixes: FS#1197 and probably others Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
95 lines
2.8 KiB
Diff
95 lines
2.8 KiB
Diff
From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Tue, 19 Jul 2016 18:44:49 +0530
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Subject: PCI: qcom: Fixed IPQ806x specific clocks
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Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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---
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drivers/pci/host/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++++-----
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1 file changed, 33 insertions(+), 5 deletions(-)
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--- a/drivers/pci/host/pcie-qcom.c
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+++ b/drivers/pci/host/pcie-qcom.c
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@@ -53,6 +53,8 @@ struct qcom_pcie_resources_v0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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struct clk *phy_clk;
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+ struct clk *aux_clk;
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+ struct clk *ref_clk;
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struct reset_control *pci_reset;
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struct reset_control *axi_reset;
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struct reset_control *ahb_reset;
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@@ -160,6 +162,14 @@ static int qcom_pcie_get_resources_v0(st
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if (IS_ERR(res->phy_clk))
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return PTR_ERR(res->phy_clk);
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+ res->aux_clk = devm_clk_get(dev, "aux");
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+ if (IS_ERR(res->aux_clk))
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+ return PTR_ERR(res->aux_clk);
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+
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+ res->ref_clk = devm_clk_get(dev, "ref");
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+ if (IS_ERR(res->ref_clk))
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+ return PTR_ERR(res->ref_clk);
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+
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res->pci_reset = devm_reset_control_get(dev, "pci");
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if (IS_ERR(res->pci_reset))
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return PTR_ERR(res->pci_reset);
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@@ -227,6 +237,8 @@ static void qcom_pcie_deinit_v0(struct q
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clk_disable_unprepare(res->iface_clk);
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clk_disable_unprepare(res->core_clk);
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clk_disable_unprepare(res->phy_clk);
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+ clk_disable_unprepare(res->aux_clk);
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+ clk_disable_unprepare(res->ref_clk);
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regulator_disable(res->vdda);
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regulator_disable(res->vdda_phy);
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regulator_disable(res->vdda_refclk);
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@@ -269,16 +281,28 @@ static int qcom_pcie_init_v0(struct qcom
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goto err_assert_ahb;
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}
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+ ret = clk_prepare_enable(res->core_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable core clock\n");
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+ goto err_clk_core;
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+ }
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+
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ret = clk_prepare_enable(res->phy_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable phy clock\n");
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goto err_clk_phy;
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}
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- ret = clk_prepare_enable(res->core_clk);
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+ ret = clk_prepare_enable(res->aux_clk);
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if (ret) {
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- dev_err(dev, "cannot prepare/enable core clock\n");
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- goto err_clk_core;
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+ dev_err(dev, "cannot prepare/enable aux clock\n");
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+ goto err_clk_aux;
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+ }
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+
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+ ret = clk_prepare_enable(res->ref_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable ref clock\n");
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+ goto err_clk_ref;
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}
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ret = reset_control_deassert(res->ahb_reset);
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@@ -327,10 +351,14 @@ static int qcom_pcie_init_v0(struct qcom
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return 0;
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err_deassert_ahb:
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- clk_disable_unprepare(res->core_clk);
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-err_clk_core:
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+ clk_disable_unprepare(res->ref_clk);
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+err_clk_ref:
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+ clk_disable_unprepare(res->aux_clk);
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+err_clk_aux:
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clk_disable_unprepare(res->phy_clk);
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err_clk_phy:
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+ clk_disable_unprepare(res->core_clk);
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+err_clk_core:
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clk_disable_unprepare(res->iface_clk);
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err_assert_ahb:
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regulator_disable(res->vdda_phy);
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