34a422794d
This backports multiple patches from kernel 4.10 which are adding missing support for the A64 and the pine64 board. These are the device tree files, the pinctlk and the clock driver. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
From 07fe64ba213f36ca8f6ffd8c4d5893f022744fdb Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Tue, 11 Oct 2016 17:46:01 +0200
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Subject: pinctrl: sunxi: Handle bias disable
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So far, putting NO_PULL in allwinner,pull was ignored, behaving like if
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that property was not there at all.
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Obviously, this is not the right thing to do, and in that case, we really
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need to just disable the bias.
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Acked-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/sunxi/pinctrl-sunxi.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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@@ -165,6 +165,8 @@ static int sunxi_pctrl_parse_bias_prop(s
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return -EINVAL;
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switch (val) {
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+ case SUN4I_PINCTRL_NO_PULL:
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+ return PIN_CONFIG_BIAS_DISABLE;
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case SUN4I_PINCTRL_PULL_UP:
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return PIN_CONFIG_BIAS_PULL_UP;
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case SUN4I_PINCTRL_PULL_DOWN:
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@@ -401,6 +403,12 @@ static int sunxi_pconf_group_set(struct
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| dlevel << sunxi_dlevel_offset(pin),
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pctl->membase + sunxi_dlevel_reg(pin));
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break;
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+ case PIN_CONFIG_BIAS_DISABLE:
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+ val = readl(pctl->membase + sunxi_pull_reg(pin));
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+ mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
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+ writel((val & ~mask),
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+ pctl->membase + sunxi_pull_reg(pin));
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+ break;
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case PIN_CONFIG_BIAS_PULL_UP:
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val = readl(pctl->membase + sunxi_pull_reg(pin));
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mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
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