182 lines
5.2 KiB
Diff
182 lines
5.2 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
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@@ -131,8 +131,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0cf0e0e0),
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.papdRateMaskHt40 = LE32(0x6cf0e0e0),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext1 = {
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@@ -331,8 +332,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0c80c080),
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.papdRateMaskHt40 = LE32(0x0080c080),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext2 = {
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@@ -704,8 +706,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0c80c080),
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.papdRateMaskHt40 = LE32(0x0080c080),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext1 = {
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@@ -904,8 +907,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0cf0e0e0),
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.papdRateMaskHt40 = LE32(0x6cf0e0e0),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext2 = {
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@@ -1278,8 +1282,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0c80c080),
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.papdRateMaskHt40 = LE32(0x0080c080),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext1 = {
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@@ -1478,8 +1483,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0cf0e0e0),
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.papdRateMaskHt40 = LE32(0x6cf0e0e0),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext2 = {
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@@ -1852,8 +1858,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0c80c080),
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.papdRateMaskHt40 = LE32(0x0080c080),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext1 = {
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@@ -2052,8 +2059,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0cf0e0e0),
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.papdRateMaskHt40 = LE32(0x6cf0e0e0),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext2 = {
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@@ -2425,8 +2433,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0c80C080),
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.papdRateMaskHt40 = LE32(0x0080C080),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext1 = {
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@@ -2625,8 +2634,9 @@ static const struct ar9300_eeprom ar9300
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.thresh62 = 28,
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.papdRateMaskHt20 = LE32(0x0cf0e0e0),
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.papdRateMaskHt40 = LE32(0x6cf0e0e0),
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+ .xlna_bias_strength = 0,
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.futureModal = {
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- 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0,
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},
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},
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.base_ext2 = {
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@@ -3942,6 +3952,28 @@ static void ar9003_hw_xpa_timing_control
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AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
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}
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+static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
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+{
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+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
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+ u8 bias;
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+
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+ if (!(eep->baseEepHeader.featureEnable & 0x40))
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+ return;
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+
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+ if (!AR_SREV_9300(ah))
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+ return;
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+
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+ bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
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+ REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
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+ bias & 0x3);
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+ bias >>= 2;
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+ REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
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+ bias & 0x3);
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+ bias >>= 2;
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+ REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
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+ bias & 0x3);
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+}
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+
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static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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@@ -3950,6 +3982,7 @@ static void ath9k_hw_ar9300_set_board_va
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ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
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ar9003_hw_ant_ctrl_apply(ah, is2ghz);
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ar9003_hw_drive_strength_apply(ah);
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+ ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
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ar9003_hw_atten_apply(ah, chan);
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ar9003_hw_quick_drop_apply(ah, chan->channel);
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if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
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--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
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@@ -231,7 +231,8 @@ struct ar9300_modal_eep_header {
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__le32 papdRateMaskHt20;
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__le32 papdRateMaskHt40;
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__le16 switchcomspdt;
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- u8 futureModal[8];
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+ u8 xlna_bias_strength;
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+ u8 futureModal[7];
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} __packed;
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struct ar9300_cal_data_per_freq_op_loop {
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--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
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@@ -633,6 +633,8 @@
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#define AR_PHY_65NM_CH0_BIAS2 0x160c4
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#define AR_PHY_65NM_CH0_BIAS4 0x160cc
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#define AR_PHY_65NM_CH0_RXTX4 0x1610c
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+#define AR_PHY_65NM_CH1_RXTX4 0x1650c
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+#define AR_PHY_65NM_CH2_RXTX4 0x1690c
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#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
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((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
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@@ -876,6 +878,9 @@
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#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
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#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
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+#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
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+#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
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+
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/*
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* Channel 1 Register Map
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*/
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