9aa196e0f2
Refresh patches, following required reworking: ar71xx/patches-4.9/930-chipidea-pullup.patch layerscape/patches-4.9/302-dts-support-layercape.patch sunxi/patches-4.9/0052-stmmac-form-4-12.patch Fixes for CVEs: CVE-2018-1108 CVE-2018-1092 Tested on: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Arjen de Korte <build+openwrt@de-korte.org>
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 5209e1b8f78fd1184f25cf19cf0daa58f4ad6599 Mon Sep 17 00:00:00 2001
|
|
From: Boris Brezillon <boris.brezillon@free-electrons.com>
|
|
Date: Thu, 1 Dec 2016 22:00:20 +0100
|
|
Subject: [PATCH] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC
|
|
clock
|
|
|
|
The VEC clock requires needs to be set at exactly 108MHz. Allow rate
|
|
change propagation on PLLH_AUX to match this requirement wihtout
|
|
impacting other IPs (PLLH is currently only used by the HDMI encoder,
|
|
which cannot be enabled when the VEC encoder is enabled).
|
|
|
|
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
|
|
Reviewed-by: Eric Anholt <eric@anholt.net>
|
|
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
(cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd)
|
|
---
|
|
drivers/clk/bcm/clk-bcm2835.c | 7 ++++++-
|
|
1 file changed, 6 insertions(+), 1 deletion(-)
|
|
|
|
--- a/drivers/clk/bcm/clk-bcm2835.c
|
|
+++ b/drivers/clk/bcm/clk-bcm2835.c
|
|
@@ -1876,7 +1876,12 @@ static const struct bcm2835_clk_desc clk
|
|
.ctl_reg = CM_VECCTL,
|
|
.div_reg = CM_VECDIV,
|
|
.int_bits = 4,
|
|
- .frac_bits = 0),
|
|
+ .frac_bits = 0,
|
|
+ /*
|
|
+ * Allow rate change propagation only on PLLH_AUX which is
|
|
+ * assigned index 7 in the parent array.
|
|
+ */
|
|
+ .set_rate_parent = BIT(7)),
|
|
|
|
/* dsi clocks */
|
|
[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
|