7e20e4ab96
Refreshed all patches. Removed upstreamed hunks in: - 703-phy-support-layerscape.patch Compile-tested on: ar71xx, layerscape Runtime-tested on: ar71xx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
124 lines
3.8 KiB
Diff
124 lines
3.8 KiB
Diff
From 8feb8081c74d15ce368baa42981ca98e77800c03 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
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Date: Fri, 23 Sep 2016 18:24:38 +0200
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Subject: [PATCH] i2c: bcm2835: Protect against unexpected TXW/RXR interrupts
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0),
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the driver has no way to fill/drain the FIFO to stop the interrupts.
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In this case the controller has to be disabled and the transfer
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completed to avoid hang.
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(CLKT | ERR) and DONE interrupts are completed in their own paths, and
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the controller is disabled in the transfer function after completion.
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Unite the code paths and do disabling inside the interrupt routine.
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Clear interrupt status bits in the united completion path instead of
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trying to do it on every interrupt which isn't necessary.
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Only CLKT, ERR and DONE can be cleared that way.
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Add the status value to the error value in case of TXW/RXR errors to
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distinguish them from the other S_LEN error.
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Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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---
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drivers/i2c/busses/i2c-bcm2835.c | 40 +++++++++++++++++++++++++++++++---------
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1 file changed, 31 insertions(+), 9 deletions(-)
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--- a/drivers/i2c/busses/i2c-bcm2835.c
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+++ b/drivers/i2c/busses/i2c-bcm2835.c
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@@ -50,8 +50,6 @@
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#define BCM2835_I2C_S_CLKT BIT(9)
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#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
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-#define BCM2835_I2C_BITMSK_S 0x03FF
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-
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#define BCM2835_I2C_CDIV_MIN 0x0002
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#define BCM2835_I2C_CDIV_MAX 0xFFFE
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@@ -111,20 +109,26 @@ static void bcm2835_drain_rxfifo(struct
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}
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}
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+/*
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+ * Note about I2C_C_CLEAR on error:
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+ * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
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+ * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
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+ * the state machine to send a NACK and a STOP. Since we're setting CLEAR
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+ * without I2CEN, that NACK will be hanging around queued up for next time
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+ * we start the engine.
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+ */
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+
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static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
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{
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struct bcm2835_i2c_dev *i2c_dev = data;
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u32 val, err;
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val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
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- val &= BCM2835_I2C_BITMSK_S;
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- bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, val);
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err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
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if (err) {
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i2c_dev->msg_err = err;
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- complete(&i2c_dev->completion);
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- return IRQ_HANDLED;
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+ goto complete;
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}
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if (val & BCM2835_I2C_S_DONE) {
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@@ -139,21 +143,38 @@ static irqreturn_t bcm2835_i2c_isr(int t
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i2c_dev->msg_err = BCM2835_I2C_S_LEN;
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else
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i2c_dev->msg_err = 0;
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- complete(&i2c_dev->completion);
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- return IRQ_HANDLED;
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+ goto complete;
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}
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if (val & BCM2835_I2C_S_TXW) {
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+ if (!i2c_dev->msg_buf_remaining) {
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+ i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
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+ goto complete;
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+ }
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+
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bcm2835_fill_txfifo(i2c_dev);
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return IRQ_HANDLED;
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}
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if (val & BCM2835_I2C_S_RXR) {
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+ if (!i2c_dev->msg_buf_remaining) {
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+ i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
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+ goto complete;
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+ }
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+
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bcm2835_drain_rxfifo(i2c_dev);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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+
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+complete:
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+ bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
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+ bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
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+ BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
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+ complete(&i2c_dev->completion);
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+
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+ return IRQ_HANDLED;
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}
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static int bcm2835_i2c_xfer_msg(struct bcm2835_i2c_dev *i2c_dev,
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@@ -183,8 +204,9 @@ static int bcm2835_i2c_xfer_msg(struct b
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time_left = wait_for_completion_timeout(&i2c_dev->completion,
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BCM2835_I2C_TIMEOUT);
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- bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
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if (!time_left) {
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+ bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
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+ BCM2835_I2C_C_CLEAR);
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dev_err(i2c_dev->dev, "i2c transfer timed out\n");
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return -ETIMEDOUT;
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}
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