56 lines
1.8 KiB
Diff
56 lines
1.8 KiB
Diff
From: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
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Date: Fri, 3 Jul 2015 11:45:42 +0530
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Subject: [PATCH] ath10k: Delay device access after cold reset
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It is observed that during cold reset pcie access right
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after a write operation to SOC_GLOBAL_RESET_ADDRESS causes
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Data Bus Error and system hard lockup. The reason
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for bus error is that pcie needs some time to get
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back to stable state for any transaction during cold reset. Add
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delay of 20 msecs after write of SOC_GLOBAL_RESET_ADDRESS
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to fix this issue.
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Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
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---
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--- a/drivers/net/wireless/ath/ath10k/pci.c
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+++ b/drivers/net/wireless/ath/ath10k/pci.c
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@@ -2602,7 +2602,6 @@ static int ath10k_pci_wait_for_target_in
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static int ath10k_pci_cold_reset(struct ath10k *ar)
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{
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- int i;
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u32 val;
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ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
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@@ -2618,23 +2617,18 @@ static int ath10k_pci_cold_reset(struct
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val |= 1;
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ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
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- for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
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- if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
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- RTC_STATE_COLD_RESET_MASK)
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- break;
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- msleep(1);
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- }
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+ /* After writing into SOC_GLOBAL_RESET to put device into
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+ * reset and pulling out of reset pcie may not be stable
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+ * for any immediate pcie register access and cause bus error,
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+ * add delay before any pcie access request to fix this issue.
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+ */
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+ msleep(20);
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/* Pull Target, including PCIe, out of RESET. */
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val &= ~1;
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ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
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- for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
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- if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
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- RTC_STATE_COLD_RESET_MASK))
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- break;
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- msleep(1);
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- }
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+ msleep(20);
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ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
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