9aa196e0f2
Refresh patches, following required reworking: ar71xx/patches-4.9/930-chipidea-pullup.patch layerscape/patches-4.9/302-dts-support-layercape.patch sunxi/patches-4.9/0052-stmmac-form-4-12.patch Fixes for CVEs: CVE-2018-1108 CVE-2018-1092 Tested on: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Arjen de Korte <build+openwrt@de-korte.org>
45 lines
1.5 KiB
Diff
45 lines
1.5 KiB
Diff
From 492d6b9c3f1f8cc1eb890dc0eafacae51d6ba2f0 Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Fri, 2 Sep 2016 16:45:27 +0100
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Subject: [PATCH] Register the clocks early during the boot process, so that
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special/critical clocks can get enabled early on in the boot process avoiding
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the risk of disabling a clock, pll_divider or pll when a claiming driver
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fails to install propperly - maybe it needs to defer.
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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---
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drivers/clk/bcm/clk-bcm2835.c | 15 +++++++++++++--
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1 file changed, 13 insertions(+), 2 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1909,8 +1909,15 @@ static int bcm2835_clk_probe(struct plat
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if (ret)
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return ret;
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- return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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+ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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&cprman->onecell);
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+ if (ret)
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+ return ret;
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+
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+ /* note that we have registered all the clocks */
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+ dev_dbg(dev, "registered %d clocks\n", asize);
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+
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+ return 0;
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}
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static const struct of_device_id bcm2835_clk_of_match[] = {
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@@ -1927,7 +1934,11 @@ static struct platform_driver bcm2835_cl
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.probe = bcm2835_clk_probe,
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};
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-builtin_platform_driver(bcm2835_clk_driver);
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+static int __init __bcm2835_clk_driver_init(void)
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+{
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+ return platform_driver_register(&bcm2835_clk_driver);
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+}
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+core_initcall(__bcm2835_clk_driver_init);
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MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
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MODULE_DESCRIPTION("BCM2835 clock driver");
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