3c1f6e358d
Patches are generated using the "format-patch" command from the following location: *https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base *rev=0771849495b4128cac2faf7d49c85c729fc48b20 Patches numbered 76/77/102/103 have already been integrated in 3.14.12, so they're not in this list. All these patches are either integrated are pending integration into kernel.org, therefore these patches should go away once the kernel gets upgraded to 3.16. Support is currently limited to AP148 board but can be extended to other platforms in the future. These changes do not cover ethernet connectivity. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 42334
268 lines
6.7 KiB
Diff
268 lines
6.7 KiB
Diff
From 881200420e6ece87d9abbb13c0653d26455cdbdd Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Wed, 28 May 2014 12:09:53 -0500
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Subject: [PATCH 092/182] ARM: dts: qcom: Update msm8960 device trees
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* Move SoC peripherals into an SoC container node
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* Move serial enabling into board file (qcom-msm8960-cdp.dts)
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* Cleanup cpu node to match binding spec, enable-method and compatible
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should be per cpu, not part of the container
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* Drop interrupts property from l2-cache node as its not part of the
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binding spec
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* Add GSBI node and configuration of GSBI controller
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++
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arch/arm/boot/dts/qcom-msm8960.dtsi | 176 ++++++++++++++++++--------------
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2 files changed, 108 insertions(+), 78 deletions(-)
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diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
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index a58fb88..8f75cc4 100644
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--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
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+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
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@@ -3,4 +3,14 @@
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/ {
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model = "Qualcomm MSM8960 CDP";
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compatible = "qcom,msm8960-cdp", "qcom,msm8960";
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+
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+ soc {
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+ gsbi@16400000 {
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+ status = "ok";
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+ qcom,mode = <GSBI_PROT_I2C_UART>;
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+ serial@16440000 {
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+ status = "ok";
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+ };
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+ };
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+ };
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};
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diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
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index 997b7b9..5303e53 100644
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--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
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+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
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@@ -3,6 +3,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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+#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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model = "Qualcomm MSM8960";
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@@ -13,10 +14,10 @@
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <1 14 0x304>;
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- compatible = "qcom,krait";
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- enable-method = "qcom,kpss-acc-v1";
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cpu@0 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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@@ -25,6 +26,8 @@
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};
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cpu@1 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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@@ -35,7 +38,6 @@
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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- interrupts = <0 2 0x4>;
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};
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};
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@@ -45,91 +47,109 @@
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qcom,no-pc-write;
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};
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- intc: interrupt-controller@2000000 {
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- compatible = "qcom,msm-qgic2";
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- interrupt-controller;
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- #interrupt-cells = <3>;
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- reg = < 0x02000000 0x1000 >,
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- < 0x02002000 0x1000 >;
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- };
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+ soc: soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "simple-bus";
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+
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+ intc: interrupt-controller@2000000 {
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+ compatible = "qcom,msm-qgic2";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = <0x02000000 0x1000>,
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+ <0x02002000 0x1000>;
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+ };
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- timer@200a000 {
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- compatible = "qcom,kpss-timer", "qcom,msm-timer";
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- interrupts = <1 1 0x301>,
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- <1 2 0x301>,
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- <1 3 0x301>;
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- reg = <0x0200a000 0x100>;
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- clock-frequency = <27000000>,
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- <32768>;
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- cpu-offset = <0x80000>;
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- };
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+ timer@200a000 {
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+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
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+ interrupts = <1 1 0x301>,
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+ <1 2 0x301>,
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+ <1 3 0x301>;
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+ reg = <0x0200a000 0x100>;
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+ clock-frequency = <27000000>,
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+ <32768>;
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+ cpu-offset = <0x80000>;
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+ };
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- msmgpio: gpio@800000 {
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- compatible = "qcom,msm-gpio";
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- gpio-controller;
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- #gpio-cells = <2>;
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- ngpio = <150>;
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- interrupts = <0 16 0x4>;
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- interrupt-controller;
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- #interrupt-cells = <2>;
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- reg = <0x800000 0x4000>;
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- };
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+ msmgpio: gpio@800000 {
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+ compatible = "qcom,msm-gpio";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ ngpio = <150>;
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+ interrupts = <0 16 0x4>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ reg = <0x800000 0x4000>;
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+ };
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- gcc: clock-controller@900000 {
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- compatible = "qcom,gcc-msm8960";
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- reg = <0x900000 0x4000>;
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- };
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+ gcc: clock-controller@900000 {
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+ compatible = "qcom,gcc-msm8960";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ reg = <0x900000 0x4000>;
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+ };
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- clock-controller@4000000 {
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- compatible = "qcom,mmcc-msm8960";
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- reg = <0x4000000 0x1000>;
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- };
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+ clock-controller@4000000 {
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+ compatible = "qcom,mmcc-msm8960";
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+ reg = <0x4000000 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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- acc0: clock-controller@2088000 {
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- compatible = "qcom,kpss-acc-v1";
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- reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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- };
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+ acc0: clock-controller@2088000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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+ };
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- acc1: clock-controller@2098000 {
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- compatible = "qcom,kpss-acc-v1";
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- reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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- };
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+ acc1: clock-controller@2098000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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+ };
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- saw0: regulator@2089000 {
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- compatible = "qcom,saw2";
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- reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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- regulator;
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- };
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+ saw0: regulator@2089000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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- saw1: regulator@2099000 {
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- compatible = "qcom,saw2";
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- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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- regulator;
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- };
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+ saw1: regulator@2099000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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- serial@16440000 {
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- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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- reg = <0x16440000 0x1000>,
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- <0x16400000 0x1000>;
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- interrupts = <0 154 0x0>;
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- clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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- clock-names = "core", "iface";
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- };
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+ gsbi5: gsbi@16400000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x16400000 0x100>;
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+ clocks = <&gcc GSBI5_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ serial@16440000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x16440000 0x1000>,
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+ <0x16400000 0x1000>;
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+ interrupts = <0 154 0x0>;
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+ clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+ };
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- qcom,ssbi@500000 {
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- compatible = "qcom,ssbi";
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- reg = <0x500000 0x1000>;
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- qcom,controller-type = "pmic-arbiter";
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- };
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+ qcom,ssbi@500000 {
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+ compatible = "qcom,ssbi";
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+ reg = <0x500000 0x1000>;
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+ qcom,controller-type = "pmic-arbiter";
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+ };
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- rng@1a500000 {
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- compatible = "qcom,prng";
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- reg = <0x1a500000 0x200>;
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- clocks = <&gcc PRNG_CLK>;
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- clock-names = "core";
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+ rng@1a500000 {
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+ compatible = "qcom,prng";
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+ reg = <0x1a500000 0x200>;
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+ clocks = <&gcc PRNG_CLK>;
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+ clock-names = "core";
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+ };
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};
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};
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--
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1.7.10.4
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