416 lines
9.7 KiB
C
416 lines
9.7 KiB
C
/*
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* Atheros AR71xx SoC specific interrupt handling
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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static void ar71xx_gpio_irq_dispatch(void)
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{
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void __iomem *base = ar71xx_gpio_base;
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u32 pending;
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pending = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING) &
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__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
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if (pending)
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do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
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else
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spurious_interrupt();
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}
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static void ar71xx_gpio_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE;
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void __iomem *base = ar71xx_gpio_base;
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u32 t;
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t = __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_GPIO_REG_INT_ENABLE);
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/* flush write */
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(void) __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
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}
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static void ar71xx_gpio_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE;
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void __iomem *base = ar71xx_gpio_base;
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u32 t;
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t = __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_GPIO_REG_INT_ENABLE);
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/* flush write */
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(void) __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
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}
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static struct irq_chip ar71xx_gpio_irq_chip = {
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.name = "AR71XX GPIO",
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.irq_unmask = ar71xx_gpio_irq_unmask,
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.irq_mask = ar71xx_gpio_irq_mask,
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.irq_mask_ack = ar71xx_gpio_irq_mask,
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};
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static struct irqaction ar71xx_gpio_irqaction = {
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.handler = no_action,
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.name = "cascade [AR71XX GPIO]",
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};
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#define GPIO_INT_ALL 0xffff
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static void __init ar71xx_gpio_irq_init(void)
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{
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void __iomem *base = ar71xx_gpio_base;
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int i;
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__raw_writel(0, base + AR71XX_GPIO_REG_INT_ENABLE);
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__raw_writel(0, base + AR71XX_GPIO_REG_INT_PENDING);
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/* setup type of all GPIO interrupts to level sensitive */
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__raw_writel(GPIO_INT_ALL, base + AR71XX_GPIO_REG_INT_TYPE);
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/* setup polarity of all GPIO interrupts to active high */
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__raw_writel(GPIO_INT_ALL, base + AR71XX_GPIO_REG_INT_POLARITY);
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for (i = AR71XX_GPIO_IRQ_BASE;
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i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &ar71xx_gpio_irq_chip,
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handle_level_irq);
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setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
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}
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static void ar71xx_misc_irq_dispatch(void)
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{
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u32 pending;
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pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
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& ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (pending & MISC_INT_UART)
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do_IRQ(AR71XX_MISC_IRQ_UART);
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else if (pending & MISC_INT_DMA)
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do_IRQ(AR71XX_MISC_IRQ_DMA);
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else if (pending & MISC_INT_PERFC)
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do_IRQ(AR71XX_MISC_IRQ_PERFC);
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else if (pending & MISC_INT_TIMER)
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do_IRQ(AR71XX_MISC_IRQ_TIMER);
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else if (pending & MISC_INT_OHCI)
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do_IRQ(AR71XX_MISC_IRQ_OHCI);
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else if (pending & MISC_INT_ERROR)
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do_IRQ(AR71XX_MISC_IRQ_ERROR);
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else if (pending & MISC_INT_GPIO)
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ar71xx_gpio_irq_dispatch();
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else if (pending & MISC_INT_WDOG)
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do_IRQ(AR71XX_MISC_IRQ_WDOG);
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else if (pending & MISC_INT_TIMER2)
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do_IRQ(AR71XX_MISC_IRQ_TIMER2);
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else if (pending & MISC_INT_TIMER3)
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do_IRQ(AR71XX_MISC_IRQ_TIMER3);
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else if (pending & MISC_INT_TIMER4)
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do_IRQ(AR71XX_MISC_IRQ_TIMER4);
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else if (pending & MISC_INT_DDR_PERF)
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do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
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else if (pending & MISC_INT_ENET_LINK)
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do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
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else
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spurious_interrupt();
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}
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static void ar71xx_misc_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
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void __iomem *base = ar71xx_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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(void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
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void __iomem *base = ar71xx_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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(void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(struct irq_data *d)
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{
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unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
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void __iomem *base = ar71xx_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/* flush write */
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(void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ar71xx_misc_irq_chip = {
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.name = "AR71XX MISC",
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.irq_unmask = ar71xx_misc_irq_unmask,
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.irq_mask = ar71xx_misc_irq_mask,
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};
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static struct irqaction ar71xx_misc_irqaction = {
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.handler = no_action,
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.name = "cascade [AR71XX MISC]",
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};
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static void __init ar71xx_misc_irq_init(void)
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{
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void __iomem *base = ar71xx_reset_base;
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int i;
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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case AR71XX_SOC_AR9330:
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case AR71XX_SOC_AR9331:
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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ar71xx_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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break;
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default:
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ar71xx_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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break;
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}
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for (i = AR71XX_MISC_IRQ_BASE;
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &ar71xx_misc_irq_chip,
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handle_level_irq);
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setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
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}
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static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ar71xx_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
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if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
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ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
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generic_handle_irq(AR934X_IP2_IRQ_PCIE);
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} else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
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ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
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generic_handle_irq(AR934X_IP2_IRQ_WMAC);
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} else {
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spurious_interrupt();
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}
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enable_irq(irq);
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}
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static void ar934x_ip2_irq_init(void)
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{
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int i;
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for (i = AR934X_IP2_IRQ_BASE;
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i < AR934X_IP2_IRQ_BASE + AR934X_IP2_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
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}
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/*
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* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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* these devices typically allocate coherent DMA memory, however the
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* DMA controller may still have some unsynchronized data in the FIFO.
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* Issue a flush in the handlers to ensure that the driver sees
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* the update.
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*/
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static void ar71xx_ip2_handler(void)
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{
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI);
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do_IRQ(AR71XX_CPU_IRQ_IP2);
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}
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static void ar724x_ip2_handler(void)
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{
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ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
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do_IRQ(AR71XX_CPU_IRQ_IP2);
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}
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static void ar913x_ip2_handler(void)
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{
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
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do_IRQ(AR71XX_CPU_IRQ_IP2);
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}
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static void ar933x_ip2_handler(void)
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{
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
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do_IRQ(AR71XX_CPU_IRQ_IP2);
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}
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static void ar934x_ip2_handler(void)
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{
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do_IRQ(AR71XX_CPU_IRQ_IP2);
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}
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static void ar71xx_ip3_handler(void)
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{
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_USB);
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do_IRQ(AR71XX_CPU_IRQ_USB);
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}
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static void ar724x_ip3_handler(void)
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{
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ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB);
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do_IRQ(AR71XX_CPU_IRQ_USB);
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}
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static void ar913x_ip3_handler(void)
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{
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
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do_IRQ(AR71XX_CPU_IRQ_USB);
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}
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static void ar933x_ip3_handler(void)
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{
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB);
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do_IRQ(AR71XX_CPU_IRQ_USB);
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}
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static void ar934x_ip3_handler(void)
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{
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do_IRQ(AR71XX_CPU_IRQ_USB);
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}
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static void (*ip2_handler)(void);
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static void (*ip3_handler)(void);
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(AR71XX_CPU_IRQ_TIMER);
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else if (pending & STATUSF_IP2)
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ip2_handler();
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else if (pending & STATUSF_IP4)
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do_IRQ(AR71XX_CPU_IRQ_GE0);
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else if (pending & STATUSF_IP5)
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do_IRQ(AR71XX_CPU_IRQ_GE1);
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else if (pending & STATUSF_IP3)
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ip3_handler();
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else if (pending & STATUSF_IP6)
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ar71xx_misc_irq_dispatch();
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else
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spurious_interrupt();
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}
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void __init arch_init_irq(void)
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{
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ip2_handler = ar71xx_ip2_handler;
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ip3_handler = ar71xx_ip3_handler;
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break;
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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ip2_handler = ar724x_ip2_handler;
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ip3_handler = ar724x_ip3_handler;
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ip2_handler = ar913x_ip2_handler;
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ip3_handler = ar913x_ip3_handler;
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break;
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case AR71XX_SOC_AR9330:
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case AR71XX_SOC_AR9331:
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ip2_handler = ar933x_ip2_handler;
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ip3_handler = ar933x_ip3_handler;
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break;
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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ip2_handler = ar934x_ip2_handler;
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ip3_handler = ar934x_ip3_handler;
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break;
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default:
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BUG();
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}
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mips_cpu_irq_init();
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ar71xx_misc_irq_init();
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if (ar71xx_soc == AR71XX_SOC_AR9341 ||
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ar71xx_soc == AR71XX_SOC_AR9342 ||
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ar71xx_soc == AR71XX_SOC_AR9344)
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ar934x_ip2_irq_init();
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cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
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ar71xx_gpio_irq_init();
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}
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