6adc757097
To mitigate this problem, the original message has been wrapped automatically by the mailing list software. This patch fixes a problem where the AR8035 PHY can't be detected on the Cisco Meraki MR24, when the ethernet cable is not connected during boot. Russell Senior reported: |This appears to be a problem during probing of the AR8035 |phy chip. When ethernet has no link, the phy detection fails, |and eth0 is not created. Plugging ethernet later has no effect, |because there is no interface as far as the kernel is |concerned. The relevant part of the boot log looks like this: | |[ 0.876611] /plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode |[ 0.882532] /plb/opb/ethernet@ef600c00: reset timeout |[ 0.888546] /plb/opb/ethernet@ef600c00: can't find PHY! (<https://bugs.lede-project.org/index.php?do=details&task_id=687>) Fixes FS#687 Cc: Chris Blake <chrisrblake93@gmail.com> Reported-by: Russell Senior <russell@personaltelco.net> Fixes: 23fbb5a87c56e98 ("emac: Fix EMAC soft reset on 460EX/GT") Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
112 lines
4.6 KiB
Diff
112 lines
4.6 KiB
Diff
From b2e79053e7456a961249c8865214a1e95b49c863 Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@googlemail.com>
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Date: Sat, 3 Jun 2017 18:16:19 +0200
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Subject: [PATCH] net: emac: fix reset timeout with AR8035 phy
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This patch fixes a problem where the AR8035 PHY can't be
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detected on an Cisco Meraki MR24, if the ethernet cable is
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not connected on boot.
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Russell Senior provided steps to reproduce the issue:
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|Disconnect ethernet cable, apply power, wait until device has booted,
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|plug in ethernet, check for interfaces, no eth0 is listed.
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|This appears to be a problem during probing of the AR8035 Phy chip.
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|When ethernet has no link, the phy detection fails, and eth0 is not
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|created. Plugging ethernet later has no effect, because there is no
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|interface as far as the kernel is concerned. The relevant part of
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|the boot log looks like this:
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|this is the failing case:
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|[ 0.876611] /plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode
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|[ 0.882532] /plb/opb/ethernet@ef600c00: reset timeout
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|[ 0.888546] /plb/opb/ethernet@ef600c00: can't find PHY!
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|and the succeeding case:
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|[ 0.876672] /plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode
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|[ 0.883952] eth0: EMAC-0 /plb/opb/ethernet@ef600c00, MAC 00:01:..
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|[ 0.890822] eth0: found Atheros 8035 Gigabit Ethernet PHY (0x01)
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Based on the comment and the commit message of
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commit 23fbb5a87c56 ("emac: Fix EMAC soft reset on 460EX/GT").
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This is because the AR8035 PHY doesn't provide the TX Clock,
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if the ethernet cable is not attached. This causes the reset
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to timeout and the PHY detection code in emac_init_phy() is
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unable to detect the AR8035 PHY. As a result, the emac driver
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bails out early and the user left with no ethernet.
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In order to stay compatible with existing configurations, the driver
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tries the current reset approach at first. Only if the first attempt
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timed out, it does perform one more retry with the clock input
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temporarily switched to the internal clock source for just the
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duration of the reset.
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LEDE-Bug: #687 <https://bugs.lede-project.org/index.php?do=details&task_id=687>
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Cc: Chris Blake <chrisrblake93@gmail.com>
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Reported-by: Russell Senior <russell@personaltelco.net>
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Fixes: 23fbb5a87c56e98 ("emac: Fix EMAC soft reset on 460EX/GT")
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
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---
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drivers/net/ethernet/ibm/emac/core.c | 26 ++++++++++++++++++++++----
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1 file changed, 22 insertions(+), 4 deletions(-)
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--- a/drivers/net/ethernet/ibm/emac/core.c
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+++ b/drivers/net/ethernet/ibm/emac/core.c
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@@ -352,6 +352,7 @@ static int emac_reset(struct emac_instan
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{
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struct emac_regs __iomem *p = dev->emacp;
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int n = 20;
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+ bool __maybe_unused try_internal_clock = false;
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DBG(dev, "reset" NL);
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@@ -364,6 +365,7 @@ static int emac_reset(struct emac_instan
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}
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#ifdef CONFIG_PPC_DCR_NATIVE
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+do_retry:
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/*
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* PPC460EX/GT Embedded Processor Advanced User's Manual
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* section 28.10.1 Mode Register 0 (EMACx_MR0) states:
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@@ -371,10 +373,19 @@ static int emac_reset(struct emac_instan
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* of the EMAC. If none is present, select the internal clock
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* (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
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* After a soft reset, select the external clock.
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+ *
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+ * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
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+ * ethernet cable is not attached. This causes the reset to timeout
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+ * and the PHY detection code in emac_init_phy() is unable to
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+ * communicate and detect the AR8035-A PHY. As a result, the emac
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+ * driver bails out early and the user has no ethernet.
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+ * In order to stay compatible with existing configurations, the
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+ * driver will temporarily switch to the internal clock, after
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+ * the first reset fails.
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*/
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if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
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- if (dev->phy_address == 0xffffffff &&
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- dev->phy_map == 0xffffffff) {
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+ if (try_internal_clock || (dev->phy_address == 0xffffffff &&
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+ dev->phy_map == 0xffffffff)) {
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/* No PHY: select internal loop clock before reset */
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dcri_clrset(SDR0, SDR0_ETH_CFG,
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0, SDR0_ETH_CFG_ECS << dev->cell_index);
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@@ -392,8 +403,15 @@ static int emac_reset(struct emac_instan
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#ifdef CONFIG_PPC_DCR_NATIVE
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if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
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- if (dev->phy_address == 0xffffffff &&
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- dev->phy_map == 0xffffffff) {
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+ if (!n && !try_internal_clock) {
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+ /* first attempt has timed out. */
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+ n = 20;
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+ try_internal_clock = true;
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+ goto do_retry;
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+ }
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+
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+ if (try_internal_clock || (dev->phy_address == 0xffffffff &&
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+ dev->phy_map == 0xffffffff)) {
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/* No PHY: restore external clock source after reset */
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dcri_clrset(SDR0, SDR0_ETH_CFG,
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SDR0_ETH_CFG_ECS << dev->cell_index, 0);
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