17f60b1cd2
Without patch unloading the dwc3-of-simple module went stuck after successfully removing hcd.1 during the hcd.0 removal: root@LEDE:/# rmmod dwc3-of-simple [ 21.391846] xhci-hcd xhci-hcd.1.auto: remove, state 1 [ 21.391931] usb usb4: USB disconnect, device number 1 [ 21.397038] xhci-hcd xhci-hcd.1.auto: USB bus 4 deregistered [ 21.401111] xhci-hcd xhci-hcd.1.auto: remove, state 1 [ 21.406685] usb usb3: USB disconnect, device number 1 [ 21.412848] xhci-hcd xhci-hcd.1.auto: USB bus 3 deregistered [ 21.417248] xhci-hcd xhci-hcd.0.auto: remove, state 1 [ 21.422521] usb usb2: USB disconnect, device number 1 followed by nothing. Sometimes a stall CPU was detected, or a kernel panic, or a reboot occurred after a couple of minutes. At the same time unloading the dwc3 module followed by dwc3-of-simple module was working repeatedly. root@LEDE:/# rmmod dwc3 [ 53.827328] xhci-hcd xhci-hcd.1.auto: remove, state 1 [ 53.827412] usb usb4: USB disconnect, device number 1 [ 53.832630] xhci-hcd xhci-hcd.1.auto: USB bus 4 deregistered [ 53.836452] xhci-hcd xhci-hcd.1.auto: remove, state 1 [ 53.842314] usb usb3: USB disconnect, device number 1 [ 53.848412] xhci-hcd xhci-hcd.1.auto: USB bus 3 deregistered [ 53.852542] xhci-hcd xhci-hcd.0.auto: remove, state 1 [ 53.857882] usb usb2: USB disconnect, device number 1 [ 53.863956] xhci-hcd xhci-hcd.0.auto: USB bus 2 deregistered [ 53.867875] xhci-hcd xhci-hcd.0.auto: remove, state 1 [ 53.873696] usb usb1: USB disconnect, device number 1 [ 53.879742] xhci-hcd xhci-hcd.0.auto: USB bus 1 deregistered root@LEDE:/# rmmod dwc3-of-simple root@LEDE:/# For the non-working case, the code was stuck in a readl() in http://lxr.free-electrons.com/source/drivers/usb/host/xhci.c#L91 because http://lxr.free-electrons.com/source/drivers/usb/dwc3/dwc3-of-simple.c#L126 was disabling the wrong clocks when removing hcd.1 (it was disabling the clock of hcd.0). That's why the readl() went stuck when removing hcd.0 The patch however addresses the clock assignment from the .dtsi file. Most probably it went into openwrt here: https://dev.openwrt.org/browser/trunk/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch?rev=45261 copied from Qualcomms attempt here: https://lkml.org/lkml/2015/11/20/116 Now unloading and repeated module loading is working just fine, no matter if you'd remove dwc3-of-simple or dwc3. root@LEDE:/# rmmod dwc3-of-simple [ 24.089679] xhci-hcd xhci-hcd.1.auto: remove, state 1 [ 24.089765] usb usb4: USB disconnect, device number 1 [ 24.094856] xhci-hcd xhci-hcd.1.auto: USB bus 4 deregistered [ 24.098963] xhci-hcd xhci-hcd.1.auto: remove, state 1 [ 24.104522] usb usb3: USB disconnect, device number 1 [ 24.111194] xhci-hcd xhci-hcd.1.auto: USB bus 3 deregistered [ 24.115086] xhci-hcd xhci-hcd.0.auto: remove, state 1 [ 24.120396] usb usb2: USB disconnect, device number 1 [ 24.126503] xhci-hcd xhci-hcd.0.auto: USB bus 2 deregistered [ 24.130347] xhci-hcd xhci-hcd.0.auto: remove, state 1 [ 24.135948] usb usb1: USB disconnect, device number 1 [ 24.142085] xhci-hcd xhci-hcd.0.auto: USB bus 1 deregistered root@LEDE:/# Fixes: dwc3-of-simple module unloading Signed-off-by: Thomas Reifferscheid <thomas@reifferscheid.org>
1321 lines
28 KiB
Text
1321 lines
28 KiB
Text
/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/mfd/qcom-rpm.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm IPQ8064";
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compatible = "qcom,ipq8064";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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clocks = <&kraitcc 0>, <&kraitcc 4>;
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clock-names = "cpu", "l2";
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clock-latency = <100000>;
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cpu-supply = <&smb208_s2a>;
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voltage-tolerance = <5>;
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cooling-min-state = <0>;
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cooling-max-state = <10>;
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#cooling-cells = <2>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu1: cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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clocks = <&kraitcc 1>, <&kraitcc 4>;
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clock-names = "cpu", "l2";
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clock-latency = <100000>;
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cpu-supply = <&smb208_s2b>;
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cooling-min-state = <0>;
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cooling-max-state = <10>;
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#cooling-cells = <2>;
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cpu-idle-states = <&CPU_SPC>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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qcom,saw = <&saw_l2>;
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};
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qcom,l2 {
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qcom,l2-rates = <384000000 1000000000 1200000000>;
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};
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idle-states {
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CPU_SPC: spc {
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compatible = "qcom,idle-state-spc",
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"arm,idle-state";
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entry-latency-us = <400>;
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exit-latency-us = <900>;
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min-residency-us = <3000>;
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};
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};
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};
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thermal-zones {
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tsens_tz_sensor0 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 0>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor1 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 1>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor2 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 2>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor3 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 3>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor4 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 4>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor5 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 5>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor6 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 6>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor7 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 7>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor8 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 8>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor9 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 9>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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tsens_tz_sensor10 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 10>;
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trips {
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cpu-critical-hi {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical_high";
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};
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cpu-config-hi {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "configurable_hi";
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};
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cpu-config-lo {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "configurable_lo";
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};
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cpu-critical-low {
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temperature = <0>;
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hysteresis = <2000>;
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type = "critical_low";
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};
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};
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 10 0x304>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nss@40000000 {
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reg = <0x40000000 0x1000000>;
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no-map;
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};
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smem: smem@41000000 {
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reg = <0x41000000 0x200000>;
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no-map;
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};
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};
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clocks {
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cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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pxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq806x";
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};
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};
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kraitcc: clock-controller {
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compatible = "qcom,krait-cc-v1";
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#clock-cells = <1>;
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};
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qcom,pvs {
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qcom,pvs-format-a;
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qcom,speed0-pvs0-bin-v0 =
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< 1400000000 1250000 >,
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< 1200000000 1200000 >,
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< 1000000000 1150000 >,
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< 800000000 1100000 >,
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< 600000000 1050000 >,
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< 384000000 1000000 >;
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qcom,speed0-pvs1-bin-v0 =
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< 1400000000 1175000 >,
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< 1200000000 1125000 >,
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< 1000000000 1075000 >,
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< 800000000 1025000 >,
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< 600000000 975000 >,
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< 384000000 925000 >;
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qcom,speed0-pvs2-bin-v0 =
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< 1400000000 1125000 >,
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< 1200000000 1075000 >,
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< 1000000000 1025000 >,
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< 800000000 995000 >,
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< 600000000 925000 >,
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< 384000000 875000 >;
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qcom,speed0-pvs3-bin-v0 =
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< 1400000000 1050000 >,
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< 1200000000 1000000 >,
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< 1000000000 950000 >,
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< 800000000 900000 >,
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< 600000000 850000 >,
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< 384000000 800000 >;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
|
|
compatible = "simple-bus";
|
|
|
|
lpass@28100000 {
|
|
compatible = "qcom,lpass-cpu";
|
|
status = "disabled";
|
|
clocks = <&lcc AHBIX_CLK>,
|
|
<&lcc MI2S_OSR_CLK>,
|
|
<&lcc MI2S_BIT_CLK>;
|
|
clock-names = "ahbix-clk",
|
|
"mi2s-osr-clk",
|
|
"mi2s-bit-clk";
|
|
interrupts = <0 85 1>;
|
|
interrupt-names = "lpass-irq-lpaif";
|
|
reg = <0x28100000 0x10000>;
|
|
reg-names = "lpass-lpaif";
|
|
};
|
|
|
|
qfprom: qfprom@700000 {
|
|
compatible = "qcom,qfprom", "syscon";
|
|
reg = <0x700000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "okay";
|
|
tsens_calib: calib@400 {
|
|
reg = <0x400 0x10>;
|
|
};
|
|
tsens_backup: backup@410 {
|
|
reg = <0x410 0x10>;
|
|
};
|
|
};
|
|
|
|
rpm@108000 {
|
|
compatible = "qcom,rpm-ipq8064";
|
|
reg = <0x108000 0x1000>;
|
|
qcom,ipc = <&l2cc 0x8 2>;
|
|
|
|
interrupts = <0 19 0>,
|
|
<0 21 0>,
|
|
<0 22 0>;
|
|
interrupt-names = "ack",
|
|
"err",
|
|
"wakeup";
|
|
|
|
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
|
|
clock-names = "ram";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
rpmcc: clock-controller {
|
|
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
regulators {
|
|
compatible = "qcom,rpm-smb208-regulators";
|
|
|
|
smb208_s1a: s1a {
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1150000>;
|
|
|
|
qcom,switch-mode-frequency = <1200000>;
|
|
|
|
};
|
|
|
|
smb208_s1b: s1b {
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1150000>;
|
|
|
|
qcom,switch-mode-frequency = <1200000>;
|
|
};
|
|
|
|
smb208_s2a: s2a {
|
|
regulator-min-microvolt = < 800000>;
|
|
regulator-max-microvolt = <1250000>;
|
|
|
|
qcom,switch-mode-frequency = <1200000>;
|
|
};
|
|
|
|
smb208_s2b: s2b {
|
|
regulator-min-microvolt = < 800000>;
|
|
regulator-max-microvolt = <1250000>;
|
|
|
|
qcom,switch-mode-frequency = <1200000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rng@1a500000 {
|
|
compatible = "qcom,prng";
|
|
reg = <0x1a500000 0x200>;
|
|
clocks = <&gcc PRNG_CLK>;
|
|
clock-names = "core";
|
|
};
|
|
|
|
qcom_pinmux: pinmux@800000 {
|
|
compatible = "qcom,ipq8064-pinctrl";
|
|
reg = <0x800000 0x4000>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <0 16 0x4>;
|
|
|
|
pcie0_pins: pcie0_pinmux {
|
|
mux {
|
|
pins = "gpio3";
|
|
function = "pcie1_rst";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie1_pins: pcie1_pinmux {
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "pcie2_rst";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie2_pins: pcie2_pinmux {
|
|
mux {
|
|
pins = "gpio63";
|
|
function = "pcie3_rst";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@2000000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x02000000 0x1000>,
|
|
<0x02002000 0x1000>;
|
|
};
|
|
|
|
timer@200a000 {
|
|
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
|
interrupts = <1 1 0x301>,
|
|
<1 2 0x301>,
|
|
<1 3 0x301>,
|
|
<1 4 0x301>,
|
|
<1 5 0x301>;
|
|
reg = <0x0200a000 0x100>;
|
|
clock-frequency = <25000000>,
|
|
<32768>;
|
|
clocks = <&sleep_clk>;
|
|
clock-names = "sleep";
|
|
cpu-offset = <0x80000>;
|
|
};
|
|
|
|
acc0: clock-controller@2088000 {
|
|
compatible = "qcom,kpss-acc-v1";
|
|
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
|
clock-output-names = "acpu0_aux";
|
|
};
|
|
|
|
acc1: clock-controller@2098000 {
|
|
compatible = "qcom,kpss-acc-v1";
|
|
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
|
clock-output-names = "acpu1_aux";
|
|
};
|
|
|
|
l2cc: clock-controller@2011000 {
|
|
compatible = "qcom,kpss-gcc", "syscon";
|
|
reg = <0x2011000 0x1000>;
|
|
clock-output-names = "acpu_l2_aux";
|
|
};
|
|
|
|
saw0: regulator@2089000 {
|
|
compatible = "qcom,saw2", "syscon";
|
|
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
|
regulator;
|
|
};
|
|
|
|
saw1: regulator@2099000 {
|
|
compatible = "qcom,saw2", "syscon";
|
|
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
|
regulator;
|
|
};
|
|
|
|
saw_l2: regulator@02012000 {
|
|
compatible = "qcom,saw2", "syscon";
|
|
reg = <0x02012000 0x1000>;
|
|
regulator;
|
|
};
|
|
|
|
sic_non_secure: sic-non-secure@12100000 {
|
|
compatible = "syscon";
|
|
reg = <0x12100000 0x10000>;
|
|
};
|
|
|
|
gsbi2: gsbi@12480000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <2>;
|
|
reg = <0x12480000 0x100>;
|
|
clocks = <&gcc GSBI2_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
uart2: serial@12490000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x12490000 0x1000>,
|
|
<0x12480000 0x1000>;
|
|
interrupts = <0 195 0x0>;
|
|
clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@124a0000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x124a0000 0x1000>;
|
|
interrupts = <0 196 0>;
|
|
|
|
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
};
|
|
|
|
gsbi4: gsbi@16300000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <4>;
|
|
reg = <0x16300000 0x100>;
|
|
clocks = <&gcc GSBI4_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
gsbi4_serial: serial@16340000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x16340000 0x1000>,
|
|
<0x16300000 0x1000>;
|
|
interrupts = <0 152 0x0>;
|
|
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@16380000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x16380000 0x1000>;
|
|
interrupts = <0 153 0>;
|
|
|
|
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
gsbi5: gsbi@1a200000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <5>;
|
|
reg = <0x1a200000 0x100>;
|
|
clocks = <&gcc GSBI5_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
uart5: serial@1a240000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x1a240000 0x1000>,
|
|
<0x1a200000 0x1000>;
|
|
interrupts = <0 154 0x0>;
|
|
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@1a280000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x1a280000 0x1000>;
|
|
interrupts = <0 155 0>;
|
|
|
|
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spi@1a280000 {
|
|
compatible = "qcom,spi-qup-v1.1.1";
|
|
reg = <0x1a280000 0x1000>;
|
|
interrupts = <0 155 0>;
|
|
|
|
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
sata_phy: sata-phy@1b400000 {
|
|
compatible = "qcom,ipq806x-sata-phy";
|
|
reg = <0x1b400000 0x200>;
|
|
|
|
clocks = <&gcc SATA_PHY_CFG_CLK>;
|
|
clock-names = "cfg";
|
|
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata@29000000 {
|
|
compatible = "qcom,ipq806x-ahci", "generic-ahci";
|
|
reg = <0x29000000 0x180>;
|
|
|
|
interrupts = <0 209 0x0>;
|
|
|
|
clocks = <&gcc SFAB_SATA_S_H_CLK>,
|
|
<&gcc SATA_H_CLK>,
|
|
<&gcc SATA_A_CLK>,
|
|
<&gcc SATA_RXOOB_CLK>,
|
|
<&gcc SATA_PMALIVE_CLK>;
|
|
clock-names = "slave_face", "iface", "core",
|
|
"rxoob", "pmalive";
|
|
|
|
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
|
|
assigned-clock-rates = <100000000>, <100000000>;
|
|
|
|
phys = <&sata_phy>;
|
|
phy-names = "sata-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
qcom,ssbi@500000 {
|
|
compatible = "qcom,ssbi";
|
|
reg = <0x00500000 0x1000>;
|
|
qcom,controller-type = "pmic-arbiter";
|
|
};
|
|
|
|
gcc: clock-controller@900000 {
|
|
compatible = "qcom,gcc-ipq8064";
|
|
reg = <0x00900000 0x4000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
tsens: thermal-sensor@900000 {
|
|
compatible = "qcom,ipq8064-tsens";
|
|
reg = <0x900000 0x3680>;
|
|
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
|
nvmem-cell-names = "calib", "calib_backup";
|
|
interrupts = <0 178 0>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@1a400000 {
|
|
compatible = "qcom,tcsr-ipq8064", "syscon";
|
|
reg = <0x1a400000 0x100>;
|
|
};
|
|
|
|
lcc: clock-controller@28000000 {
|
|
compatible = "qcom,lcc-ipq8064";
|
|
reg = <0x28000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
sfpb_mutex_block: syscon@1200600 {
|
|
compatible = "syscon";
|
|
reg = <0x01200600 0x100>;
|
|
};
|
|
|
|
hs_phy_1: phy@110f8800 {
|
|
compatible = "qcom,dwc3-hs-usb-phy";
|
|
reg = <0x110f8800 0x30>;
|
|
clocks = <&gcc USB30_1_UTMI_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ss_phy_1: phy@110f8830 {
|
|
compatible = "qcom,dwc3-ss-usb-phy";
|
|
reg = <0x110f8830 0x30>;
|
|
clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
hs_phy_0: phy@100f8800 {
|
|
compatible = "qcom,dwc3-hs-usb-phy";
|
|
reg = <0x100f8800 0x30>;
|
|
clocks = <&gcc USB30_0_UTMI_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ss_phy_0: phy@100f8830 {
|
|
compatible = "qcom,dwc3-ss-usb-phy";
|
|
reg = <0x100f8830 0x30>;
|
|
clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_0: usb30@0 {
|
|
compatible = "qcom,dwc3";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
clock-names = "core";
|
|
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
dwc3@10000000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x10000000 0xcd00>;
|
|
interrupts = <0 205 0x4>;
|
|
phys = <&hs_phy_0>, <&ss_phy_0>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
dr_mode = "host";
|
|
snps,dis_u3_susphy_quirk;
|
|
};
|
|
};
|
|
|
|
usb3_1: usb30@1 {
|
|
compatible = "qcom,dwc3";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
clock-names = "core";
|
|
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
dwc3@11000000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x11000000 0xcd00>;
|
|
interrupts = <0 110 0x4>;
|
|
phys = <&hs_phy_1>, <&ss_phy_1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
dr_mode = "host";
|
|
snps,dis_u3_susphy_quirk;
|
|
};
|
|
};
|
|
|
|
pcie0: pci@1b500000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b500000 0x1000
|
|
0x1b502000 0x80
|
|
0x1b600000 0x100
|
|
0x0ff00000 0x100000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
|
|
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
|
|
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc PCIE_A_CLK>,
|
|
<&gcc PCIE_H_CLK>,
|
|
<&gcc PCIE_PHY_CLK>,
|
|
<&gcc PCIE_AUX_CLK>,
|
|
<&gcc PCIE_ALT_REF_CLK>;
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc PCIE_ACLK_RESET>,
|
|
<&gcc PCIE_HCLK_RESET>,
|
|
<&gcc PCIE_POR_RESET>,
|
|
<&gcc PCIE_PCI_RESET>,
|
|
<&gcc PCIE_PHY_RESET>,
|
|
<&gcc PCIE_EXT_RESET>;
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
pinctrl-0 = <&pcie0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pci@1b700000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b700000 0x1000
|
|
0x1b702000 0x80
|
|
0x1b800000 0x100
|
|
0x31f00000 0x100000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <1>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
|
|
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
|
|
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc PCIE_1_A_CLK>,
|
|
<&gcc PCIE_1_H_CLK>,
|
|
<&gcc PCIE_1_PHY_CLK>,
|
|
<&gcc PCIE_1_AUX_CLK>,
|
|
<&gcc PCIE_1_ALT_REF_CLK>;
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc PCIE_1_ACLK_RESET>,
|
|
<&gcc PCIE_1_HCLK_RESET>,
|
|
<&gcc PCIE_1_POR_RESET>,
|
|
<&gcc PCIE_1_PCI_RESET>,
|
|
<&gcc PCIE_1_PHY_RESET>,
|
|
<&gcc PCIE_1_EXT_RESET>;
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
pinctrl-0 = <&pcie1_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie2: pci@1b900000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b900000 0x1000
|
|
0x1b902000 0x80
|
|
0x1ba00000 0x100
|
|
0x35f00000 0x100000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <2>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
|
|
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
|
|
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc PCIE_2_A_CLK>,
|
|
<&gcc PCIE_2_H_CLK>,
|
|
<&gcc PCIE_2_PHY_CLK>,
|
|
<&gcc PCIE_2_AUX_CLK>,
|
|
<&gcc PCIE_2_ALT_REF_CLK>;
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc PCIE_2_ACLK_RESET>,
|
|
<&gcc PCIE_2_HCLK_RESET>,
|
|
<&gcc PCIE_2_POR_RESET>,
|
|
<&gcc PCIE_2_PCI_RESET>,
|
|
<&gcc PCIE_2_PHY_RESET>,
|
|
<&gcc PCIE_2_EXT_RESET>;
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
pinctrl-0 = <&pcie2_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
adm_dma: dma@18300000 {
|
|
compatible = "qcom,adm";
|
|
reg = <0x18300000 0x100000>;
|
|
interrupts = <0 170 0>;
|
|
#dma-cells = <1>;
|
|
|
|
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
resets = <&gcc ADM0_RESET>,
|
|
<&gcc ADM0_PBUS_RESET>,
|
|
<&gcc ADM0_C0_RESET>,
|
|
<&gcc ADM0_C1_RESET>,
|
|
<&gcc ADM0_C2_RESET>;
|
|
reset-names = "clk", "pbus", "c0", "c1", "c2";
|
|
qcom,ee = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
nand@1ac00000 {
|
|
compatible = "qcom,ipq806x-nand";
|
|
reg = <0x1ac00000 0x800>;
|
|
|
|
clocks = <&gcc EBI2_CLK>,
|
|
<&gcc EBI2_AON_CLK>;
|
|
clock-names = "core", "aon";
|
|
|
|
dmas = <&adm_dma 3>;
|
|
dma-names = "rxtx";
|
|
qcom,cmd-crci = <15>;
|
|
qcom,data-crci = <3>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
nss_common: syscon@03000000 {
|
|
compatible = "syscon";
|
|
reg = <0x03000000 0x0000FFFF>;
|
|
};
|
|
|
|
qsgmii_csr: syscon@1bb00000 {
|
|
compatible = "syscon";
|
|
reg = <0x1bb00000 0x000001FF>;
|
|
};
|
|
|
|
stmmac_axi_setup: stmmac-axi-config {
|
|
snps,wr_osr_lmt = <7>;
|
|
snps,rd_osr_lmt = <7>;
|
|
snps,blen = <16 0 0 0 0 0 0>;
|
|
};
|
|
|
|
gmac0: ethernet@37000000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac";
|
|
reg = <0x37000000 0x200000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal = <1>;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE1_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE1_RESET>;
|
|
reset-names = "stmmaceth";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac1: ethernet@37200000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac";
|
|
reg = <0x37200000 0x200000>;
|
|
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal = <1>;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE2_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE2_RESET>;
|
|
reset-names = "stmmaceth";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac2: ethernet@37400000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac";
|
|
reg = <0x37400000 0x200000>;
|
|
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal = <1>;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE3_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE3_RESET>;
|
|
reset-names = "stmmaceth";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac3: ethernet@37600000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac";
|
|
reg = <0x37600000 0x200000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal = <1>;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE4_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE4_RESET>;
|
|
reset-names = "stmmaceth";
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sfpb_mutex: sfpb-mutex {
|
|
compatible = "qcom,sfpb-mutex";
|
|
syscon = <&sfpb_mutex_block 4 4>;
|
|
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem>;
|
|
hwlocks = <&sfpb_mutex 3>;
|
|
};
|
|
};
|