58 lines
1.7 KiB
Diff
58 lines
1.7 KiB
Diff
From 0aff0370cbffeadc14456556b904c80e30b3717e Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Wed, 1 Jan 2014 10:30:48 +0800
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Subject: [PATCH] ARM: dts: sun7i: external clock outputs
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This commit adds the two external clock outputs available on A20 to
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its device tree. A dummy fixed factor clock is also added to serve as
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the first input of the clock outputs, which according to AW's A20 user
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manual, is the 24MHz oscillator divided by 750.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++
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1 file changed, 28 insertions(+)
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diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
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index edad6f1..0d54998 100644
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -303,6 +303,34 @@
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clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
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clock-output-names = "mbus";
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};
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+
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+ /*
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+ * Dummy clock used by output clocks
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+ */
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+ osc24M_32k: clk@1 {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clock-div = <750>;
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+ clock-mult = <1>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "osc24M_32k";
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+ };
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+
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+ clk_out_a: clk@01c201f0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun7i-a20-out-clk";
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+ reg = <0x01c201f0 0x4>;
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+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
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+ clock-output-names = "clk_out_a";
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+ };
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+
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+ clk_out_b: clk@01c201f4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun7i-a20-out-clk";
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+ reg = <0x01c201f4 0x4>;
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+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
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+ clock-output-names = "clk_out_b";
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+ };
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};
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soc@01c00000 {
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--
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1.8.5.5
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