112 lines
3.5 KiB
Diff
112 lines
3.5 KiB
Diff
--- a/include/asm-mips/io.h
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+++ b/include/asm-mips/io.h
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@@ -118,12 +118,12 @@ static inline void set_io_port_base(unsi
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* Change virtual addresses to physical addresses and vv.
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* These are trivial on the 1:1 Linux/MIPS mapping
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*/
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-extern inline phys_addr_t virt_to_phys(volatile void * address)
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+static inline phys_addr_t virt_to_phys(volatile void * address)
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{
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return CPHYSADDR(address);
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}
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-extern inline void * phys_to_virt(unsigned long address)
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+static inline void * phys_to_virt(unsigned long address)
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{
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return (void *)KSEG0ADDR(address);
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}
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@@ -131,12 +131,12 @@ extern inline void * phys_to_virt(unsign
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/*
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* IO bus memory addresses are also 1:1 with the physical address
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*/
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-extern inline unsigned long virt_to_bus(volatile void * address)
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+static inline unsigned long virt_to_bus(volatile void * address)
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{
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return CPHYSADDR(address);
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}
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-extern inline void * bus_to_virt(unsigned long address)
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+static inline void * bus_to_virt(unsigned long address)
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{
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return (void *)KSEG0ADDR(address);
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}
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@@ -150,12 +150,12 @@ extern unsigned long isa_slot_offset;
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extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
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#if 0
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-extern inline void *ioremap(unsigned long offset, unsigned long size)
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+static inline void *ioremap(unsigned long offset, unsigned long size)
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{
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return __ioremap(offset, size, _CACHE_UNCACHED);
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}
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-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
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+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
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{
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return __ioremap(offset, size, _CACHE_UNCACHED);
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}
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@@ -238,7 +238,7 @@ out:
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*/
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#define __OUT1(s) \
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-extern inline void __out##s(unsigned int value, unsigned int port) {
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+static inline void __out##s(unsigned int value, unsigned int port) {
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#define __OUT2(m) \
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__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
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@@ -252,7 +252,7 @@ __OUT1(s##c_p) __OUT2(m) : : "r" (__iosw
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SLOW_DOWN_IO; }
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#define __IN1(t,s) \
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-extern __inline__ t __in##s(unsigned int port) { t _v;
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+static inline t __in##s(unsigned int port) { t _v;
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/*
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* Required nops will be inserted by the assembler
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@@ -267,7 +267,7 @@ __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i
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__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
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#define __INS1(s) \
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-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
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+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
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#define __INS2(m) \
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if (count) \
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@@ -295,7 +295,7 @@ __INS1(s##c) __INS2(m) \
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: "$1");}
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#define __OUTS1(s) \
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-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
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+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
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#define __OUTS2(m) \
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if (count) \
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--- a/include/asm-mips/system.h
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+++ b/include/asm-mips/system.h
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@@ -23,7 +23,7 @@
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#include <linux/kernel.h>
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#endif
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-extern __inline__ void
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+static inline void
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__sti(void)
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{
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__asm__ __volatile__(
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@@ -47,7 +47,7 @@ __sti(void)
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* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
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* no nops at all.
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*/
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-extern __inline__ void
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+static inline void
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__cli(void)
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{
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__asm__ __volatile__(
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@@ -208,7 +208,7 @@ do { \
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* For 32 and 64 bit operands we can take advantage of ll and sc.
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* FIXME: This doesn't work for R3000 machines.
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*/
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-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
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+static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
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{
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#ifdef CONFIG_CPU_HAS_LLSC
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unsigned long dummy;
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