e8068f0b1b
Add the required nodes for the interrupt controllers and register them through DT when a DTB is present. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 43457
62 lines
1.2 KiB
Text
62 lines
1.2 KiB
Text
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "brcm,bcm6362";
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "brcm,bmips4350", "mips,mips4Kc";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "brcm,bmips4350", "mips,mips4Kc";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
cpu_intc: interrupt-controller {
|
|
#address-cells = <0>;
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
memory { device_type = "memory"; reg = <0 0>; };
|
|
|
|
ubus@10000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "simple-bus";
|
|
|
|
ext_intc: interrupt-controller@10000018 {
|
|
compatible = "brcm,bcm6345-ext-intc";
|
|
reg = <0x10000018 0x4>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&periph_intc>;
|
|
interrupts = <40>, <41>, <42>, <43>;
|
|
};
|
|
|
|
periph_intc: interrupt-controller@10000020 {
|
|
compatible = "brcm,bcm6345-l2-intc";
|
|
reg = <0x10000020 0x10>,
|
|
<0x10000030 0x10>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-parent = <&cpu_intc>;
|
|
interrupts = <2>, <3>;
|
|
};
|
|
};
|
|
};
|