43 lines
1.4 KiB
Diff
43 lines
1.4 KiB
Diff
From 2646be877afc663d1688a2add8386b027c9d7e31 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Mon, 11 Mar 2013 14:08:06 +0100
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Subject: [PATCH 11/12] spi/bcm63xx: inline hz usage in
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bcm63xx_spi_setup_transfer
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bcm63xx_spi_setup_transfer is called from only one place, and that has
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t always set, to hz will always be t->speed_hz - just use it directly in
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the two places instead of moving it in a local variable.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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drivers/spi/spi-bcm63xx.c | 7 ++-----
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1 file changed, 2 insertions(+), 5 deletions(-)
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--- a/drivers/spi/spi-bcm63xx.c
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+++ b/drivers/spi/spi-bcm63xx.c
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@@ -97,15 +97,12 @@ static void bcm63xx_spi_setup_transfer(s
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struct spi_transfer *t)
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{
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struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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- u32 hz;
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u8 clk_cfg, reg;
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int i;
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- hz = (t) ? t->speed_hz : spi->max_speed_hz;
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-
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/* Find the closest clock configuration */
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for (i = 0; i < SPI_CLK_MASK; i++) {
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- if (hz >= bcm63xx_spi_freq_table[i][0]) {
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+ if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
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clk_cfg = bcm63xx_spi_freq_table[i][1];
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break;
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}
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@@ -122,7 +119,7 @@ static void bcm63xx_spi_setup_transfer(s
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bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
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dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
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- clk_cfg, hz);
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+ clk_cfg, t->speed_hz);
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}
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/* the spi->mode bits understood by this driver: */
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