7912677086
This is mainly a bug fix for multi-core MIPS systems where L1 caches besides the primary do not get flushed. The most obvious problem is data corruption on SATA and USB devices where read requests are typically larger than the cacheline size. This may also fix ar71xx systems that suffer from similar data corruption but I have not tested if it does. Signed-off-by: Rosen Penev <rosenp@gmail.com>
92 lines
3.6 KiB
Diff
Executable file
92 lines
3.6 KiB
Diff
Executable file
From patchwork Thu Apr 26 23:28:34 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2] MIPS: c-r4k: fix data corruption related to cache coherence.
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X-Patchwork-Submitter: NeilBrown <neil@brown.name>
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X-Patchwork-Id: 19259
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Message-Id: <87vacdlf8d.fsf@notabene.neil.brown.name>
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To: James Hogan <jhogan@kernel.org>
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Cc: Ralf Baechle <ralf@linux-mips.org>,
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Paul Burton <paul.burton@mips.com>, linux-mips@linux-mips.org,
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linux-kernel@vger.kernel.org
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Date: Fri, 27 Apr 2018 09:28:34 +1000
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From: NeilBrown <neil@brown.name>
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List-Id: linux-mips <linux-mips.eddie.linux-mips.org>
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When DMA will be performed to a MIPS32 1004K CPS, the
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L1-cache for the range needs to be flushed and invalidated
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first.
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The code currently takes one of two approaches.
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1/ If the range is less than the size of the dcache, then
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HIT type requests flush/invalidate cache lines for the
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particular addresses. HIT-type requests a globalised
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by the CPS so this is safe on SMP.
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2/ If the range is larger than the size of dcache, then
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INDEX type requests flush/invalidate the whole cache.
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INDEX type requests affect the local cache only. CPS
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does not propagate them in any way. So this invalidation
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is not safe on SMP CPS systems.
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Data corruption due to '2' can quite easily be demonstrated by
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repeatedly "echo 3 > /proc/sys/vm/drop_caches" and then sha1sum
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a file that is several times the size of available memory.
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Dropping caches means that large contiguous extents (large than
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dcache) are more likely.
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This was not a problem before Linux-4.8 because option 2 was
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never used if CONFIG_MIPS_CPS was defined. The commit
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which removed that apparently didn't appreciate the full
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consequence of the change.
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We could, in theory, globalize the INDEX based flush by sending an IPI
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to other cores. These cache invalidation routines can be called with
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interrupts disabled and synchronous IPI require interrupts to be
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enabled. Asynchronous IPI may not trigger writeback soon enough.
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So we cannot use IPI in practice.
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We can already test is IPI would be needed for an INDEX operation
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with r4k_op_needs_ipi(R4K_INDEX). If this is True then we mustn't try
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the INDEX approach as we cannot use IPI. If this is False (e.g. when
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there is only one core and hence one L1 cache) then it is safe to
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use the INDEX approach without IPI.
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This patch avoids options 2 if r4k_op_needs_ipi(R4K_INDEX), and so
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eliminates the corruption.
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Fixes: c00ab4896ed5 ("MIPS: Remove cpu_has_safe_index_cacheops")
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Cc: stable@vger.kernel.org # v4.8+
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Signed-off-by: NeilBrown <neil@brown.name>
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---
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arch/mips/mm/c-r4k.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
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index 6f534b209971..e12dfa48b478 100644
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -851,9 +851,12 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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/*
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* Either no secondary cache or the available caches don't have the
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* subset property so we have to flush the primary caches
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- * explicitly
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+ * explicitly.
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+ * If we would need IPI to perform an INDEX-type operation, then
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+ * we have to use the HIT-type alternative as IPI cannot be used
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+ * here due to interrupts possibly being disabled.
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*/
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- if (size >= dcache_size) {
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+ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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@@ -890,7 +893,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
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return;
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}
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- if (size >= dcache_size) {
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+ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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