148 lines
3.4 KiB
C
148 lines
3.4 KiB
C
#ifndef AMAZON_DMA_H
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#define AMAZON_DMA_H
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#define RCV_INT 1
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#define TX_BUF_FULL_INT 2
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#define TRANSMIT_CPT_INT 4
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#define QOS_DEFAULT_WGT 0x7fffffffUL;
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enum attr_t{
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TX=0,
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RX=1,
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RESERVED=2,
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DEFAULT=3,
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};
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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typedef struct rx_desc{
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u32 data_length:16;
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volatile u32 reserved:7;
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volatile u32 byte_offset:2;
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volatile u32 Burst_length_offset:3;
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volatile u32 EoP:1;
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volatile u32 Res:1;
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volatile u32 C:1;
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volatile u32 OWN:1;
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volatile u32 Data_Pointer;
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/*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
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}_rx_desc;
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typedef struct tx_desc{
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volatile u32 data_length:16;
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volatile u32 reserved1:7;
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volatile u32 byte_offset:5;
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volatile u32 EoP:1;
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volatile u32 SoP:1;
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volatile u32 C:1;
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volatile u32 OWN:1;
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volatile u32 Data_Pointer;//fix me:should be 28 bits here
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}_tx_desc;
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#else //BIG
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typedef struct rx_desc{
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union
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{
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struct
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{
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volatile u32 OWN :1;
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volatile u32 C :1;
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volatile u32 SoP :1;
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volatile u32 EoP :1;
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volatile u32 Burst_length_offset :3;
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volatile u32 byte_offset :2;
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volatile u32 reserve :7;
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volatile u32 data_length :16;
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}field;
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volatile u32 word;
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}status;
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volatile u32 Data_Pointer;
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}_rx_desc;
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typedef struct tx_desc{
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union
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{
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struct
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{
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volatile u32 OWN :1;
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volatile u32 C :1;
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volatile u32 SoP :1;
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volatile u32 EoP :1;
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volatile u32 byte_offset :5;
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volatile u32 reserved :7;
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volatile u32 data_length :16;
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}field;
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volatile u32 word;
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}status;
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volatile u32 Data_Pointer;
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}_tx_desc;
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#endif //ENDIAN
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struct dma_channel_info{
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/*filled by driver, optional*/
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enum attr_t attr;/*TX or RX*/
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int weight;
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int desc_num;
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int packet_size;
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int control;/*on or off*/
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int desc_base;
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int status;
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};
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typedef struct dma_channel_info _dma_channel_info;
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struct dma_device_info{
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/*variables*/
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/*filled by driver, compulsary*/
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char device_name[15];
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enum attr_t attr;/*default or else*/
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int tx_burst_len;
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int rx_burst_len;
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int logic_rx_chan_base;
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int logic_tx_chan_base;
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u8 on_ch_bit;
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/*filled by driver, optional*/
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int weight;
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int current_tx_chan;
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int current_rx_chan;
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int num_tx_chan;
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int num_rx_chan;
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struct dma_channel_info tx_chan[2];
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struct dma_channel_info rx_chan[4];
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/*functions, optional*/
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u8* (*buffer_alloc)(int len,int* offset, void** opt);
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int (*buffer_free)(u8* dataptr, void* opt);
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int (*intr_handler)(struct dma_device_info* info, int status);
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/*set by device, clear by dma*/
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int ack;
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void * priv; /* used by peripheral driver only */
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};
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typedef struct dma_device_info _dma_device_info;
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int dma_device_register(struct dma_device_info* info);
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int dma_device_unregister(struct dma_device_info* info);
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int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
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int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
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int dma_device_update(struct dma_device_info* info);
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void dma_device_update_rx(struct dma_device_info* dma_dev);
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void dma_device_update_tx(struct dma_device_info* dma_dev);
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void register_handler_sim(int (*handler)(int));
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#endif /* AMAZON_DMA_H */
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