87 lines
2.8 KiB
Diff
87 lines
2.8 KiB
Diff
From a9f5a167be625cf0cd157aa38f3635b2b1f0cc0f Mon Sep 17 00:00:00 2001
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From: Jes Sorensen <Jes.Sorensen@redhat.com>
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Date: Fri, 29 Jul 2016 15:25:34 -0400
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Subject: [PATCH] rtl8xxxu: Add some 8188eu registers and update
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CCK0_AFE_SETTING bit defines
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CCK0_AFE_SETTING is particular, it has the notion of primary RX antenna
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and optional RX antenna. When configuring RX for single antenna, setup
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should use the same antenna for default and optional. For AB setup,
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use antenna A as default and B as optional.
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In addition add info for 8188eu IOL magic interface used to send
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firmware and register init files to the firmware.
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Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
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---
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 30 ++++++++++++++++++++--
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1 file changed, 28 insertions(+), 2 deletions(-)
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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@@ -378,6 +378,11 @@
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#define PBP_PAGE_SIZE_512 0x3
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#define PBP_PAGE_SIZE_1024 0x4
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+/* 8188eu IOL magic */
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+#define REG_PKT_BUF_ACCESS_CTRL 0x0106
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+#define PKT_BUF_ACCESS_CTRL_TX 0x69
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+#define PKT_BUF_ACCESS_CTRL_RX 0xa5
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+
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#define REG_TRXDMA_CTRL 0x010c
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#define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2)
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#define TRXDMA_CTRL_VOQ_SHIFT 4
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@@ -449,6 +454,7 @@
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#define REG_FIFOPAGE 0x0204
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#define REG_TDECTRL 0x0208
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+
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#define REG_TXDMA_OFFSET_CHK 0x020c
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#define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
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#define REG_TXDMA_STATUS 0x0210
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@@ -938,6 +944,7 @@
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#define REG_FPGA1_RF_MODE 0x0900
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#define REG_FPGA1_TX_INFO 0x090c
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+#define REG_ANT_MAPPING1 0x0914
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#define REG_DPDT_CTRL 0x092c /* 8723BU */
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#define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */
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#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */
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@@ -949,9 +956,25 @@
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#define REG_CCK0_AFE_SETTING 0x0a04
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#define CCK0_AFE_RX_MASK 0x0f000000
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-#define CCK0_AFE_RX_ANT_AB BIT(24)
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+#define CCK0_AFE_TX_MASK 0xf0000000
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#define CCK0_AFE_RX_ANT_A 0
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-#define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
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+#define CCK0_AFE_RX_ANT_B BIT(26)
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+#define CCK0_AFE_RX_ANT_C BIT(27)
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+#define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27))
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+#define CCK0_AFE_RX_ANT_OPTION_A 0
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+#define CCK0_AFE_RX_ANT_OPTION_B BIT(24)
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+#define CCK0_AFE_RX_ANT_OPTION_C BIT(25)
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+#define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25))
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+#define CCK0_AFE_TX_ANT_A BIT(31)
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+#define CCK0_AFE_TX_ANT_B BIT(30)
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+
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+#define REG_CCK_ANTDIV_PARA2 0x0a04
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+#define REG_BB_POWER_SAVE4 0x0a74
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+
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+/* 8188eu */
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+#define REG_LNA_SWITCH 0x0b2c
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+#define LNA_SWITCH_DISABLE_CSCG BIT(22)
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+#define LNA_SWITCH_OUTPUT_CG BIT(31)
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#define REG_CONFIG_ANT_A 0x0b68
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#define REG_CONFIG_ANT_B 0x0b6c
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@@ -1004,6 +1027,9 @@
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#define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0
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+/* 8188eu */
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+#define REG_ANTDIV_PARA1 0x0ca4
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+
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/* 8723bu */
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#define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4
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