openwrtv4/target/linux/ramips/files/arch/mips/ralink
John Crispin 6641024f50 uart_clk on Rt3352F is always 40MHz
Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <dgolle@allnet.de>

SVN-Revision: 32812
2012-07-24 20:37:50 +00:00
..
common ramips: replace RALINK_SOC_* macros with global variables 2012-03-11 19:05:56 +00:00
rt288x ramips: replace RALINK_SOC_* macros with global variables 2012-03-11 19:05:56 +00:00
rt305x uart_clk on Rt3352F is always 40MHz 2012-07-24 20:37:50 +00:00
rt3883 ramips: rt3883: add device registration code for the SPI controller 2012-05-27 17:10:00 +00:00
Kconfig ramips: select HW_HAS_PCI on per-board basis 2012-02-16 08:17:54 +00:00
Platform ramips: add preliminary support for the RT3662/RT3883 SoCs 2012-02-13 15:17:59 +00:00