f9b8328d79
Add the ranges property to the PCI bridges where missing. Add the unit address to PCI bridge where missing. Rework the complete rt3883 pci node. Drop the PCI unit nodes from the dtsi. They are not used by any dts file and should be rather in the dts than in the SoC dtsi. Express the PCI-PCI bridge in a clean devicetree syntax. The ralink,pci-slot isn't used by any driver, drop it. Move the pci interrupt controller out of the pci node. It doesn't share the same reg and therefore should be an independent/SoC child node. Move the pci related rt3883 pinctrl setting to the dtsi instead of defining the very same for each rt3883 board. If the device_type property is used for PCI units, the unit is treated as pci bridge which it isn't. Drop it for PCI units. Reference pci-bridges or the pci node defined in the dtsi instead of recreating the whole node hierarchy. It allows to change the referenced node in the dtsi without the need to touch all dts. Fix the PCI(e) wireless unit addresses. All our PCI(e) wireless chips are the first device on the bus. The unit address has to be the bus address instead of the PCI vendor/device id. Signed-off-by: Mathias Kresin <dev@kresin.me>
100 lines
1.5 KiB
Text
100 lines
1.5 KiB
Text
/dts-v1/;
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#include "mt7628an.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "mercury,mac1200r-v2", "mediatek,mt7628an-soc";
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model = "Mercury MAC1200R v2";
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aliases {
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led-status = &led_status;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x2000000>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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led_status: status {
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label = "mac1200rv2:green:status";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0 0>;
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spi-max-frequency = <10000000>;
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m25p,chunked-io = <32>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x1d800>;
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};
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factory: partition@0x1d800 {
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label = "factory_info";
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reg = <0x1d800 0x800>;
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read-only;
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};
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art: partition@0x1e000 {
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label = "art";
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reg = <0x1e000 0x2000>;
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read-only;
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};
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partition@20000 {
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label = "config";
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reg = <0x20000 0x10000>;
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};
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partition@30000 {
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label = "u-boot2";
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reg = <0x30000 0x10000>;
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};
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partition@40000 {
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label = "firmware";
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reg = <0x40000 0x7c0000>;
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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mtd-mac-address = <&factory 0xd>;
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mediatek,portmap = "llllw";
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};
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&wmac {
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status = "okay";
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ralink,mtd-eeprom = <&art 0x0>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&art 0x1000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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