f9b8328d79
Add the ranges property to the PCI bridges where missing. Add the unit address to PCI bridge where missing. Rework the complete rt3883 pci node. Drop the PCI unit nodes from the dtsi. They are not used by any dts file and should be rather in the dts than in the SoC dtsi. Express the PCI-PCI bridge in a clean devicetree syntax. The ralink,pci-slot isn't used by any driver, drop it. Move the pci interrupt controller out of the pci node. It doesn't share the same reg and therefore should be an independent/SoC child node. Move the pci related rt3883 pinctrl setting to the dtsi instead of defining the very same for each rt3883 board. If the device_type property is used for PCI units, the unit is treated as pci bridge which it isn't. Drop it for PCI units. Reference pci-bridges or the pci node defined in the dtsi instead of recreating the whole node hierarchy. It allows to change the referenced node in the dtsi without the need to touch all dts. Fix the PCI(e) wireless unit addresses. All our PCI(e) wireless chips are the first device on the bus. The unit address has to be the bus address instead of the PCI vendor/device id. Signed-off-by: Mathias Kresin <dev@kresin.me>
150 lines
2.2 KiB
Text
150 lines
2.2 KiB
Text
/dts-v1/;
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "hiwifi,hc5962", "mediatek,mt7621-soc";
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model = "HiWiFi HC5962";
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aliases {
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led-status = &led_status;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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gpio-leds {
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compatible = "gpio-leds";
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led_status: status {
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label = "hc5962:white:status";
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gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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};
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system {
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label = "hc5962:red:system";
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gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&nand {
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status = "okay";
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "debug";
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reg = <0x80000 0x80000>;
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read-only;
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};
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factory: partition@100000 {
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label = "factory";
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reg = <0x100000 0x40000>;
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read-only;
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};
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partition@140000 {
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label = "kernel";
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reg = <0x140000 0x200000>;
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};
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partition@340000 {
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label = "ubi";
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reg = <0x340000 0x1E00000>;
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};
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partition@2140000 {
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label = "hw_panic";
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reg = <0x2140000 0x80000>;
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read-only;
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};
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partition@21c0000 {
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label = "bdinfo";
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reg = <0x21c0000 0x80000>;
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read-only;
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};
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partition@2240000 {
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label = "backup";
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reg = <0x2240000 0x80000>;
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read-only;
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};
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partition@22c0000 {
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label = "overly";
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reg = <0x22c0000 0x1000000>;
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};
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partition@32c0000 {
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label = "firmware_backup";
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reg = <0x32c0000 0x2000000>;
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};
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partition@52c0000 {
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label = "oem";
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reg = <0x52c0000 0x200000>;
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};
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partition@54c0000 {
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label = "opt";
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reg = <0x54c0000 0x2ac0000>;
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x0000>;
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&pcie1 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "uart3", "jtag";
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ralink,function = "gpio";
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};
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};
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};
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