cae808946a
Add patches and config for 4.14, refreshed from 4.9. Signed-off-by: Matti Laakso <matti.laakso@outlook.com>
47 lines
1.5 KiB
Diff
47 lines
1.5 KiB
Diff
From 981c1d416af45eff207227aec106381ac23aac99 Mon Sep 17 00:00:00 2001
|
|
From: Ian Pozella <Ian.Pozella@imgtec.com>
|
|
Date: Mon, 20 Feb 2017 10:00:52 +0000
|
|
Subject: MIPS: DTS: img: marduk: switch mmc to 1 bit mode
|
|
|
|
The mmc block in Pistachio allows 1 to 8 data bits to be used.
|
|
Marduk uses 4 bits allowing the upper 4 bits to be allocated
|
|
to the Mikrobus ports. However these bits are still connected
|
|
internally meaning the mmc block recieves signals on all data lines
|
|
and seems the internal HW CRC checks get corrupted by this erroneous
|
|
data.
|
|
|
|
We cannot control what data is sent on these lines because they go
|
|
to external ports. 1 bit mode does not exhibit the issue hence the
|
|
safe default is to use this. If a user knows that in their use case
|
|
they will not use the upper bits then they can set to 4 bit mode in
|
|
order to improve performance.
|
|
|
|
Also make sure that the upper 4 bits don't get allocated to the mmc
|
|
driver (the default is to assign all 8 pins) so they can be allocated
|
|
to other drivers. Allocating all 4 despite setting 1 bit mode as this
|
|
matches what is there in hardware.
|
|
|
|
Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com>
|
|
---
|
|
arch/mips/boot/dts/img/pistachio_marduk.dts | 3 ++-
|
|
1 file changed, 2 insertions(+), 1 deletion(-)
|
|
|
|
--- a/arch/mips/boot/dts/img/pistachio_marduk.dts
|
|
+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
|
|
@@ -120,7 +120,7 @@
|
|
|
|
&sdhost {
|
|
status = "okay";
|
|
- bus-width = <4>;
|
|
+ bus-width = <1>;
|
|
disable-wp;
|
|
};
|
|
|
|
@@ -130,6 +130,7 @@
|
|
|
|
&pin_sdhost_data {
|
|
drive-strength = <2>;
|
|
+ pins = "mfio17", "mfio18", "mfio19", "mfio20";
|
|
};
|
|
|
|
&pwm {
|