c9ae111a20
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13. This work mainly covers: * Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family, and the Armada family. * timer initialization update, and access function for the Armada family. * Generic IRQ handling backporting. * Some bug fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39566
65 lines
1.8 KiB
Diff
65 lines
1.8 KiB
Diff
From c524c5790d413b37702013e7e83a845fd3f007ac Mon Sep 17 00:00:00 2001
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From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Date: Tue, 13 Aug 2013 14:25:20 +0200
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Subject: [PATCH 200/203] PCI: mvebu: move clock enable before register access
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The clock passed to PCI controller found on MVEBU SoCs may come from a
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clock gate. This requires the clock to be enabled before any registers
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are accessed. Therefore, move the clock enable before register iomap to
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ensure it is enabled.
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Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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drivers/pci/host/pci-mvebu.c | 25 ++++++++++++-------------
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1 file changed, 12 insertions(+), 13 deletions(-)
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--- a/drivers/pci/host/pci-mvebu.c
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+++ b/drivers/pci/host/pci-mvebu.c
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@@ -896,11 +896,23 @@ static int __init mvebu_pcie_probe(struc
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continue;
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}
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+ port->clk = of_clk_get_by_name(child, NULL);
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+ if (IS_ERR(port->clk)) {
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+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
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+ port->port, port->lane);
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+ continue;
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+ }
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+
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+ ret = clk_prepare_enable(port->clk);
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+ if (ret)
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+ continue;
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+
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port->base = mvebu_pcie_map_registers(pdev, child, port);
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if (IS_ERR(port->base)) {
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dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
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port->port, port->lane);
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port->base = NULL;
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+ clk_disable_unprepare(port->clk);
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continue;
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}
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@@ -916,22 +928,9 @@ static int __init mvebu_pcie_probe(struc
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port->port, port->lane);
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}
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- port->clk = of_clk_get_by_name(child, NULL);
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- if (!port->clk) {
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- dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
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- port->port, port->lane);
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- iounmap(port->base);
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- port->haslink = 0;
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- continue;
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- }
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-
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port->dn = child;
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-
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- clk_prepare_enable(port->clk);
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spin_lock_init(&port->conf_lock);
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-
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mvebu_sw_pci_bridge_init(port);
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-
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i++;
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}
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