222 lines
5.6 KiB
Diff
222 lines
5.6 KiB
Diff
From e19957560170d63c6a5f0b1d7ba63695e4d1f033 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 2 Dec 2013 16:14:28 +0100
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Subject: [PATCH 506/507] GPIO: ralink: add mt7621 gpio controller
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/Kconfig | 1 +
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drivers/gpio/Kconfig | 6 ++
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drivers/gpio/Makefile | 1 +
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drivers/gpio/gpio-mt7621.c | 183 ++++++++++++++++++++++++++++++++++++++++++++
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4 files changed, 191 insertions(+)
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create mode 100644 drivers/gpio/gpio-mt7621.c
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -710,6 +710,12 @@ config GPIO_MSIC
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Enable support for GPIO on intel MSIC controllers found in
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intel MID devices
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+config GPIO_MT7621
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+ bool "Mediatek GPIO Support"
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+ depends on RALINK && SOC_MT7621
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+ help
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+ Say yes here to support the Mediatek SoC GPIO device
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+
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comment "USB GPIO expanders:"
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config GPIO_VIPERBOARD
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--- a/drivers/gpio/Makefile
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+++ b/drivers/gpio/Makefile
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@@ -88,3 +88,4 @@ obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x
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obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
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obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
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obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
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+obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-mt7621.c
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@@ -0,0 +1,183 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/err.h>
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+#include <linux/gpio.h>
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+#include <linux/module.h>
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+#include <linux/of_irq.h>
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+#include <linux/spinlock.h>
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+#include <linux/irqdomain.h>
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+#include <linux/interrupt.h>
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+#include <linux/platform_device.h>
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+
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+#define MTK_BANK_WIDTH 32
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+
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+enum mediatek_gpio_reg {
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+ GPIO_REG_CTRL = 0,
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+ GPIO_REG_POL,
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+ GPIO_REG_DATA,
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+ GPIO_REG_DSET,
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+ GPIO_REG_DCLR,
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+};
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+
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+static void __iomem *mtk_gc_membase;
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+
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+struct mtk_gc {
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+ struct gpio_chip chip;
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+ spinlock_t lock;
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+ int bank;
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+};
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+
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+int
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+gpio_to_irq(unsigned gpio)
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+{
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+ return -1;
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+}
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+
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+static inline struct mtk_gc
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+*to_mediatek_gpio(struct gpio_chip *chip)
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+{
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+ struct mtk_gc *mgc;
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+
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+ mgc = container_of(chip, struct mtk_gc, chip);
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+
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+ return mgc;
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+}
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+
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+static inline void
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+mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
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+{
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+ iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
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+}
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+
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+static inline u32
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+mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
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+{
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+ return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
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+}
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+
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+static void
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+mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+
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+ mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
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+}
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+
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+static int
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+mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+
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+ return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
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+}
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+
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+static int
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+mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+ unsigned long flags;
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+ u32 t;
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
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+ t &= ~BIT(offset);
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+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int
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+mediatek_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned offset, int value)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+ unsigned long flags;
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+ u32 t;
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
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+ t |= BIT(offset);
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+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
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+ mediatek_gpio_set(chip, offset, value);
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int
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+mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
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+{
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+ const __be32 *id = of_get_property(bank, "reg", NULL);
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+ struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
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+ sizeof(struct mtk_gc), GFP_KERNEL);
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+ if (!rg || !id)
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+ return -ENOMEM;
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+
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+ spin_lock_init(&rg->lock);
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+
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+ rg->chip.dev = &pdev->dev;
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+ rg->chip.label = dev_name(&pdev->dev);
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+ rg->chip.of_node = bank;
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+ rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
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+ rg->chip.ngpio = MTK_BANK_WIDTH;
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+ rg->chip.direction_input = mediatek_gpio_direction_input;
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+ rg->chip.direction_output = mediatek_gpio_direction_output;
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+ rg->chip.get = mediatek_gpio_get;
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+ rg->chip.set = mediatek_gpio_set;
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+
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+ /* set polarity to low for all gpios */
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+ mtk_gpio_w32(rg, GPIO_REG_POL, 0);
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+
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+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
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+
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+ return gpiochip_add(&rg->chip);
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+}
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+
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+static int
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+mediatek_gpio_probe(struct platform_device *pdev)
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+{
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+ struct device_node *bank, *np = pdev->dev.of_node;
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+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ mtk_gc_membase = devm_request_and_ioremap(&pdev->dev, res);
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+ if (IS_ERR(mtk_gc_membase))
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+ return PTR_ERR(mtk_gc_membase);
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+
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+ for_each_child_of_node(np, bank)
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+ if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
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+ mediatek_gpio_bank_probe(pdev, bank);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id mediatek_gpio_match[] = {
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+ { .compatible = "mtk,mt7621-gpio" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
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+
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+static struct platform_driver mediatek_gpio_driver = {
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+ .probe = mediatek_gpio_probe,
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+ .driver = {
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+ .name = "mt7621_gpio",
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+ .owner = THIS_MODULE,
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+ .of_match_table = mediatek_gpio_match,
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+ },
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+};
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+
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+static int __init
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+mediatek_gpio_init(void)
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+{
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+ return platform_driver_register(&mediatek_gpio_driver);
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+}
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+
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+subsys_initcall(mediatek_gpio_init);
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