61 lines
2 KiB
Diff
61 lines
2 KiB
Diff
From: Miaoqing Pan <miaoqing@qca.qualcomm.com>
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Date: Thu, 6 Nov 2014 10:52:23 +0530
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Subject: [PATCH] ath9k: Fix RTC_DERIVED_CLK usage
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Based on the reference clock, which could be 25MHz or 40MHz,
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AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
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But, when a chip reset is done, processing the initvals
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sets the register back to the default value.
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Fix this by moving the code in ath9k_hw_init_pll() to
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ar9003_hw_override_ini(). Also, do this override for AR9531.
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Cc: stable@vger.kernel.org
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Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
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Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
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---
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--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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@@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struc
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ah->enabled_cals |= TX_CL_CAL;
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else
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ah->enabled_cals &= ~TX_CL_CAL;
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+
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+ if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {
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+ if (ah->is_clk_25mhz) {
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+ REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
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+ REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
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+ REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
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+ } else {
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+ REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
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+ REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
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+ REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
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+ }
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+ udelay(100);
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+ }
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}
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static void ar9003_hw_prog_ini(struct ath_hw *ah,
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -870,19 +870,6 @@ static void ath9k_hw_init_pll(struct ath
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udelay(RTC_PLL_SETTLE_DELAY);
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REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
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-
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- if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
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- if (ah->is_clk_25mhz) {
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- REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
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- REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
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- REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
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- } else {
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- REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
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- REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
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- REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
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- }
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- udelay(100);
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- }
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}
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static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
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