1db4135e32
Adds preliminary kernel 4.9 support for this target. - Refreshed/Updated all patches Added 3 new patches: - 093 --> Add virtual PCI MMIO mapping - 230 --> Remove deprecated code - 240 --> Rework AT24 eeprom code to use the new NVMEM API Compiled & tested on cns3xxx (gw2388) Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
109 lines
3.5 KiB
Diff
109 lines
3.5 KiB
Diff
--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus
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return base + (where & 0xffc) + (devfn << 12);
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}
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+static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
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+{
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+ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
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+
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+ /* check PCI-compatible status register after access */
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+ if (cnspci->linked) {
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+ void __iomem *host_base;
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+ u32 sreg, ereg;
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+
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+ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
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+ sreg = __raw_readw(host_base + 0x6) & 0xF900;
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+ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
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+
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+ if (sreg | ereg) {
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+ /* SREG:
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+ * BIT15 - Detected Parity Error
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+ * BIT14 - Signaled System Error
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+ * BIT13 - Received Master Abort
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+ * BIT12 - Received Target Abort
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+ * BIT11 - Signaled Target Abort
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+ * BIT08 - Master Data Parity Error
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+ *
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+ * EREG:
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+ * BIT20 - Unsupported Request
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+ * BIT19 - ECRC
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+ * BIT18 - Malformed TLP
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+ * BIT17 - Receiver Overflow
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+ * BIT16 - Unexpected Completion
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+ * BIT15 - Completer Abort
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+ * BIT14 - Completion Timeout
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+ * BIT13 - Flow Control Protocol Error
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+ * BIT12 - Poisoned TLP
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+ * BIT04 - Data Link Protocol Error
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+ *
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+ * TODO: see Documentation/pci-error-recovery.txt
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+ * implement error_detected handler
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+ */
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+/*
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+ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
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+ if (sreg & BIT(15)) printk(" <PERR");
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+ if (sreg & BIT(14)) printk(" >SERR");
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+ if (sreg & BIT(13)) printk(" <MABRT");
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+ if (sreg & BIT(12)) printk(" <TABRT");
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+ if (sreg & BIT(11)) printk(" >TABRT");
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+ if (sreg & BIT( 8)) printk(" MPERR");
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+
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+ if (ereg & BIT(20)) printk(" Unsup");
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+ if (ereg & BIT(19)) printk(" ECRC");
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+ if (ereg & BIT(18)) printk(" MTLP");
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+ if (ereg & BIT(17)) printk(" OFLOW");
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+ if (ereg & BIT(16)) printk(" Unex");
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+ if (ereg & BIT(15)) printk(" ABRT");
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+ if (ereg & BIT(14)) printk(" COMPTO");
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+ if (ereg & BIT(13)) printk(" FLOW");
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+ if (ereg & BIT(12)) printk(" PTLP");
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+ if (ereg & BIT( 4)) printk(" DLINK");
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+ printk("\n");
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+*/
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+ pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
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+ pci_domain_nr(bus), sreg);
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+
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+ /* make sure the status bits are reset */
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+ __raw_writew(sreg, host_base + 6);
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+ __raw_writel(ereg, host_base + 0x104);
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+ return 1;
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+ }
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+ }
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+ else
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+ return 1;
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+
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+ return 0;
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+}
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+
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static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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@@ -95,6 +168,11 @@ static int cns3xxx_pci_read_config(struc
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ret = pci_generic_config_read32(bus, devfn, where, size, val);
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+ if (check_master_abort(bus, devfn, where)) {
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+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ }
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+
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if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
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(where & 0xffc) == PCI_CLASS_REVISION)
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/*
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@@ -257,8 +335,14 @@ static void __init cns3xxx_pcie_hw_init(
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static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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+#if 0
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+/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
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+ * ignore imprecise aborts and use PCI-compatible Status register to
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+ * determine errors instead
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+ */
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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+#endif
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return 0;
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}
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