eba84bee4c
The device tree file of ARV752DPW uses numbers/hex values for gpio states and input event codes. This cleans it up and uses the available macros from header files. This way the functions are easier to read and comprehend. Signed-off-by: Andreas Eberlein <foodeas@aeberlein.de> [sanitize all device tree files] Signed-off-by: Mathias Kresin <dev@kresin.me>
337 lines
6.7 KiB
Text
337 lines
6.7 KiB
Text
#include "vr9.dtsi"
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/ {
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chosen {
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bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
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};
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aliases {
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led-boot = &power;
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led-failsafe = &power;
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led-running = &power;
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led-usb = &usb1;
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led-usb2 = &usb2;
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};
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memory@0 {
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reg = <0x0 0x4000000>;
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};
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fpi@10000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,fpi", "simple-bus";
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ranges = <0x0 0x10000000 0xEEFFFFF>;
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reg = <0x10000000 0xEF00000>;
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localbus@0 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "lantiq,localbus", "simple-bus";
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};
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gpio: pinmux@E100B10 {
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compatible = "lantiq,pinctrl-xr9";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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interrupt-parent = <&icu0>;
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interrupts = <166 135 66 40 41 42 38>;
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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state_default: pinmux {
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exin3 {
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lantiq,groups = "exin3";
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lantiq,function = "exin";
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};
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stp {
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lantiq,groups = "stp";
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lantiq,function = "stp";
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};
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nand {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd", "nand rdy";
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lantiq,function = "ebu";
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};
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mdio {
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lantiq,groups = "mdio";
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lantiq,function = "mdio";
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};
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pci {
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lantiq,groups = "gnt1", "req1";
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lantiq,function = "pci";
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};
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conf_out {
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lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
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"io4", "io5", "io6", /* stp */
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"io21",
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"io33";
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lantiq,open-drain;
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lantiq,pull = <0>;
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lantiq,output = <1>;
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};
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pcie-rst {
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lantiq,pins = "io38";
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lantiq,pull = <0>;
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lantiq,output = <1>;
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};
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conf_in {
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lantiq,pins = "io39", /* exin3 */
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"io48"; /* nand rdy */
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lantiq,pull = <2>;
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};
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};
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pins_spi_default: pins_spi_default {
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spi_in {
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lantiq,groups = "spi_di";
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lantiq,function = "spi";
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};
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spi_out {
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lantiq,groups = "spi_do", "spi_clk",
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"spi_cs4";
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lantiq,function = "spi";
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lantiq,output = <1>;
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};
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};
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};
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stp: stp@E100BB0 {
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compatible = "lantiq,gpio-stp-xway";
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reg = <0xE100BB0 0x40>;
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#gpio-cells = <2>;
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gpio-controller;
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lantiq,shadow = <0xffff>;
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lantiq,groups = <0x7>;
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lantiq,dsl = <0x3>;
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lantiq,phy1 = <0x7>;
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lantiq,phy2 = <0x7>;
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/* lantiq,rising; */
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};
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ifxhcd@E101000 {
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status = "okay";
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gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
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lantiq,portmask = <0x3>;
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};
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pci@E105400 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "lantiq,pci-xway1";
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bus-range = <0x0 0x0>;
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ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
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0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
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reg = <0x7000000 0x8000 /* config space */
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0xE105400 0x400>; /* pci bridge */
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lantiq,bus-clock = <33333333>;
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/*lantiq,external-clock;*/
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lantiq,delay-hi = <0>; /* 0ns delay */
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lantiq,delay-lo = <0>; /* 0.0ns delay */
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
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>;
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gpios-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
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req-mask = <0x1>; /* GNT1 */
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};
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};
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gphy-xrx200 {
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compatible = "lantiq,phy-xrx200";
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firmware1 = "lantiq/vr9_phy11g_a1x.bin";
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firmware2 = "lantiq/vr9_phy11g_a2x.bin";
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phys = [ 00 01 ];
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <100>;
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/* reset {
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label = "reset";
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gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};*/
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paging {
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label = "paging";
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gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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power: power {
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label = "easy80920:green:power";
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gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
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default-state = "keep";
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};
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warning {
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label = "easy80920:green:warning";
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gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
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};
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fxs1 {
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label = "easy80920:green:fxs1";
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gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
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};
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fxs2 {
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label = "easy80920:green:fxs2";
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gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
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};
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fxo {
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label = "easy80920:green:fxo";
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gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
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};
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usb1: usb1 {
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label = "easy80920:green:usb1";
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gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
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};
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usb2: usb2 {
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label = "easy80920:green:usb2";
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gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
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};
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sd {
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label = "easy80920:green:sd";
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gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
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};
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wps {
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label = "easy80920:green:wps";
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gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&spi {
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pinctrl-names = "default";
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pinctrl-0 = <&pins_spi_default>;
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status = "ok";
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m25p80@4 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <4 0>;
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spi-max-frequency = <1000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x20000>;
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label = "SPI (RO) U-Boot Image";
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read-only;
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};
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partition@20000 {
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reg = <0x20000 0x10000>;
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label = "ENV_MAC";
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read-only;
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};
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partition@30000 {
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reg = <0x30000 0x10000>;
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label = "DPF";
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read-only;
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};
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partition@40000 {
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reg = <0x40000 0x10000>;
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label = "NVRAM";
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read-only;
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};
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partition@500000 {
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reg = <0x50000 0x003a0000>;
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label = "kernel";
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};
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};
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};
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};
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ð0 {
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lan: interface@0 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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lantiq,switch;
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ethernet@4 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <4>;
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phynmode0 = "gmii";
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phy-handle = <&phy13>;
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};
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ethernet@2 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <2>;
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phy-mode = "gmii";
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phy-handle = <&phy11>;
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};
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ethernet@1 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <1>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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ethernet@0 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <0>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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};
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wan: interface@1 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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lantiq,wan;
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ethernet@5 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <5>;
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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};
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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