387736af41
Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET in datasheets will trigger either a reset for builtin switch or assert an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected to external PHY/switch. None of them should be triggered every time an interface is brought up in ethernet driver. Remove PHY reset support from ag71xx and definition for them in dtsi. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> |
||
|---|---|---|
| .. | ||
| arch/mips | ||
| drivers | ||