140 lines
4.2 KiB
Diff
140 lines
4.2 KiB
Diff
commit 23d5de8efb9aed48074a72bf3d43841e1556ca42
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Author: Paul Burton <paul.burton@imgtec.com>
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Date: Tue Sep 22 11:12:16 2015 -0700
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MIPS: CM: Introduce core-other locking functions
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Introduce mips_cm_lock_other & mips_cm_unlock_other, mirroring the
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existing CPC equivalents, in order to lock access from the current core
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to another via the core-other GCR region. This hasn't been required in
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the past but with CM3 the CPC starts using GCR_CL_OTHER rather than
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CPC_CL_OTHER and this will be required for safety.
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[ralf@linux-mips.org: Fix merge conflict.]
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Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Cc: James Hogan <james.hogan@imgtec.com>
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Cc: Markos Chandras <markos.chandras@imgtec.com>
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Patchwork: https://patchwork.linux-mips.org/patch/11207/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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--- a/arch/mips/include/asm/mips-cm.h
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+++ b/arch/mips/include/asm/mips-cm.h
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@@ -334,6 +334,10 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
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/* GCR_Cx_OTHER register fields */
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#define CM_GCR_Cx_OTHER_CORENUM_SHF 16
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#define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16)
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+#define CM3_GCR_Cx_OTHER_CORE_SHF 8
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+#define CM3_GCR_Cx_OTHER_CORE_MSK (_ULCAST_(0x3f) << 8)
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+#define CM3_GCR_Cx_OTHER_VP_SHF 0
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+#define CM3_GCR_Cx_OTHER_VP_MSK (_ULCAST_(0x7) << 0)
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/* GCR_Cx_RESET_BASE register fields */
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#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12
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@@ -444,4 +448,32 @@ static inline unsigned int mips_cm_vp_id
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return (core * mips_cm_max_vp_width()) + vp;
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}
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+#ifdef CONFIG_MIPS_CM
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+
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+/**
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+ * mips_cm_lock_other - lock access to another core
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+ * @core: the other core to be accessed
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+ * @vp: the VP within the other core to be accessed
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+ *
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+ * Call before operating upon a core via the 'other' register region in
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+ * order to prevent the region being moved during access. Must be followed
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+ * by a call to mips_cm_unlock_other.
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+ */
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+extern void mips_cm_lock_other(unsigned int core, unsigned int vp);
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+
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+/**
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+ * mips_cm_unlock_other - unlock access to another core
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+ *
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+ * Call after operating upon another core via the 'other' register region.
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+ * Must be called after mips_cm_lock_other.
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+ */
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+extern void mips_cm_unlock_other(void);
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+
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+#else /* !CONFIG_MIPS_CM */
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+
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+static inline void mips_cm_lock_other(unsigned int core) { }
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+static inline void mips_cm_unlock_other(void) { }
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+
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+#endif /* !CONFIG_MIPS_CM */
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+
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#endif /* __MIPS_ASM_MIPS_CM_H__ */
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--- a/arch/mips/kernel/mips-cm.c
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+++ b/arch/mips/kernel/mips-cm.c
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@@ -9,6 +9,8 @@
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*/
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#include <linux/errno.h>
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+#include <linux/percpu.h>
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+#include <linux/spinlock.h>
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#include <asm/mips-cm.h>
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#include <asm/mipsregs.h>
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@@ -136,6 +138,9 @@ static char *cm3_causes[32] = {
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"0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
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};
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+static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
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+static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
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+
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phys_addr_t __mips_cm_phys_base(void)
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{
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u32 config3 = read_c0_config3();
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@@ -200,6 +205,7 @@ int mips_cm_probe(void)
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{
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phys_addr_t addr;
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u32 base_reg;
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+ unsigned cpu;
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/*
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* No need to probe again if we have already been
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@@ -247,9 +253,42 @@ int mips_cm_probe(void)
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/* determine register width for this CM */
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mips_cm_is64 = config_enabled(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
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+ for_each_possible_cpu(cpu)
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+ spin_lock_init(&per_cpu(cm_core_lock, cpu));
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+
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return 0;
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}
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+void mips_cm_lock_other(unsigned int core, unsigned int vp)
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+{
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+ unsigned curr_core;
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+ u32 val;
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+
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+ preempt_disable();
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+ curr_core = current_cpu_data.core;
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+ spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
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+ per_cpu(cm_core_lock_flags, curr_core));
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+
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+ if (mips_cm_revision() >= CM_REV_CM3) {
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+ val = core << CM3_GCR_Cx_OTHER_CORE_SHF;
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+ val |= vp << CM3_GCR_Cx_OTHER_VP_SHF;
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+ } else {
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+ BUG_ON(vp != 0);
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+ val = core << CM_GCR_Cx_OTHER_CORENUM_SHF;
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+ }
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+
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+ write_gcr_cl_other(val);
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+}
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+
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+void mips_cm_unlock_other(void)
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+{
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+ unsigned curr_core = current_cpu_data.core;
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+
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+ spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
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+ per_cpu(cm_core_lock_flags, curr_core));
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+ preempt_enable();
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+}
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+
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void mips_cm_error_report(void)
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{
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unsigned long revision = mips_cm_revision();
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