bdc0750191
Users reported network issues with AR8327 which turned out to be caused by EEE not working correctly with certain link partners (ticket 14597). The workaround was to disable EEE on all ports (changeset 41577). The issue was with certain link partners only, therefore this patch allows to control usage of EEE per port via swconfig. Still the default is to initially disable EEE on all ports. Successfully tested on a TL-WDR4900 (AR8327 rev.4) Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> SVN-Revision: 44021
227 lines
7.3 KiB
C
227 lines
7.3 KiB
C
/*
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* ar8327.h: AR8216 switch driver
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*
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* Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __AR8327_H
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#define __AR8327_H
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#define AR8327_NUM_PORTS 7
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#define AR8327_NUM_LEDS 15
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#define AR8327_PORTS_ALL 0x7f
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#define AR8327_NUM_LED_CTRL_REGS 4
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#define AR8327_REG_MASK 0x000
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#define AR8327_REG_PAD0_MODE 0x004
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#define AR8327_REG_PAD5_MODE 0x008
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#define AR8327_REG_PAD6_MODE 0x00c
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#define AR8327_PAD_MAC_MII_RXCLK_SEL BIT(0)
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#define AR8327_PAD_MAC_MII_TXCLK_SEL BIT(1)
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#define AR8327_PAD_MAC_MII_EN BIT(2)
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#define AR8327_PAD_MAC_GMII_RXCLK_SEL BIT(4)
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#define AR8327_PAD_MAC_GMII_TXCLK_SEL BIT(5)
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#define AR8327_PAD_MAC_GMII_EN BIT(6)
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#define AR8327_PAD_SGMII_EN BIT(7)
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#define AR8327_PAD_PHY_MII_RXCLK_SEL BIT(8)
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#define AR8327_PAD_PHY_MII_TXCLK_SEL BIT(9)
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#define AR8327_PAD_PHY_MII_EN BIT(10)
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#define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL BIT(11)
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#define AR8327_PAD_PHY_GMII_RXCLK_SEL BIT(12)
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#define AR8327_PAD_PHY_GMII_TXCLK_SEL BIT(13)
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#define AR8327_PAD_PHY_GMII_EN BIT(14)
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#define AR8327_PAD_PHYX_GMII_EN BIT(16)
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#define AR8327_PAD_PHYX_RGMII_EN BIT(17)
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#define AR8327_PAD_PHYX_MII_EN BIT(18)
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#define AR8327_PAD_SGMII_DELAY_EN BIT(19)
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#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2)
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#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20
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#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2)
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#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22
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#define AR8327_PAD_RGMII_RXCLK_DELAY_EN BIT(24)
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#define AR8327_PAD_RGMII_TXCLK_DELAY_EN BIT(25)
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#define AR8327_PAD_RGMII_EN BIT(26)
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#define AR8327_REG_POWER_ON_STRIP 0x010
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#define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31)
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#define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24)
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#define AR8327_POWER_ON_STRIP_SERDES_AEN BIT(7)
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#define AR8327_REG_INT_STATUS0 0x020
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#define AR8327_INT0_VT_DONE BIT(20)
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#define AR8327_REG_INT_STATUS1 0x024
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#define AR8327_REG_INT_MASK0 0x028
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#define AR8327_REG_INT_MASK1 0x02c
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#define AR8327_REG_MODULE_EN 0x030
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#define AR8327_MODULE_EN_MIB BIT(0)
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#define AR8327_REG_MIB_FUNC 0x034
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#define AR8327_MIB_CPU_KEEP BIT(20)
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#define AR8327_REG_SERVICE_TAG 0x048
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#define AR8327_REG_LED_CTRL(_i) (0x050 + (_i) * 4)
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#define AR8327_REG_LED_CTRL0 0x050
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#define AR8327_REG_LED_CTRL1 0x054
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#define AR8327_REG_LED_CTRL2 0x058
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#define AR8327_REG_LED_CTRL3 0x05c
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#define AR8327_REG_MAC_ADDR0 0x060
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#define AR8327_REG_MAC_ADDR1 0x064
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#define AR8327_REG_MAX_FRAME_SIZE 0x078
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#define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14)
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#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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#define AR8327_REG_HEADER_CTRL 0x098
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#define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
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#define AR8327_REG_SGMII_CTRL 0x0e0
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#define AR8327_SGMII_CTRL_EN_PLL BIT(1)
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#define AR8327_SGMII_CTRL_EN_RX BIT(2)
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#define AR8327_SGMII_CTRL_EN_TX BIT(3)
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#define AR8327_REG_EEE_CTRL 0x100
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#define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
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#define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
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#define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12)
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#define AR8327_PORT_VLAN0_DEF_SVID_S 0
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#define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12)
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#define AR8327_PORT_VLAN0_DEF_CVID_S 16
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#define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
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#define AR8327_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
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#define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2)
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#define AR8327_PORT_VLAN1_OUT_MODE_S 12
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#define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0
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#define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1
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#define AR8327_PORT_VLAN1_OUT_MODE_TAG 2
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#define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3
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#define AR8327_REG_ATU_DATA0 0x600
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#define AR8327_REG_ATU_DATA1 0x604
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#define AR8327_REG_ATU_DATA2 0x608
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#define AR8327_REG_ATU_FUNC 0x60c
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#define AR8327_ATU_FUNC_OP BITS(0, 4)
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#define AR8327_ATU_FUNC_OP_NOOP 0x0
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#define AR8327_ATU_FUNC_OP_FLUSH 0x1
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#define AR8327_ATU_FUNC_OP_LOAD 0x2
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#define AR8327_ATU_FUNC_OP_PURGE 0x3
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#define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4
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#define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5
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#define AR8327_ATU_FUNC_OP_GET_NEXT 0x6
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#define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7
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#define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8
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#define AR8327_ATU_FUNC_BUSY BIT(31)
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#define AR8327_REG_VTU_FUNC0 0x0610
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#define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14)
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#define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
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#define AR8327_VTU_FUNC0_EG_MODE_KEEP 0
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#define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1
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#define AR8327_VTU_FUNC0_EG_MODE_TAG 2
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#define AR8327_VTU_FUNC0_EG_MODE_NOT 3
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#define AR8327_VTU_FUNC0_IVL BIT(19)
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#define AR8327_VTU_FUNC0_VALID BIT(20)
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#define AR8327_REG_VTU_FUNC1 0x0614
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#define AR8327_VTU_FUNC1_OP BITS(0, 3)
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#define AR8327_VTU_FUNC1_OP_NOOP 0
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#define AR8327_VTU_FUNC1_OP_FLUSH 1
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#define AR8327_VTU_FUNC1_OP_LOAD 2
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#define AR8327_VTU_FUNC1_OP_PURGE 3
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#define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4
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#define AR8327_VTU_FUNC1_OP_GET_NEXT 5
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#define AR8327_VTU_FUNC1_OP_GET_ONE 6
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#define AR8327_VTU_FUNC1_FULL BIT(4)
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#define AR8327_VTU_FUNC1_PORT BIT(8, 4)
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#define AR8327_VTU_FUNC1_PORT_S 8
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#define AR8327_VTU_FUNC1_VID BIT(16, 12)
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#define AR8327_VTU_FUNC1_VID_S 16
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#define AR8327_VTU_FUNC1_BUSY BIT(31)
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#define AR8327_REG_FWD_CTRL0 0x620
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#define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10)
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#define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
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#define AR8327_FWD_CTRL0_MIRROR_PORT_S 4
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#define AR8327_REG_FWD_CTRL1 0x624
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#define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7)
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#define AR8327_FWD_CTRL1_UC_FLOOD_S 0
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#define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7)
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#define AR8327_FWD_CTRL1_MC_FLOOD_S 8
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#define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7)
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#define AR8327_FWD_CTRL1_BC_FLOOD_S 16
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#define AR8327_FWD_CTRL1_IGMP BITS(24, 7)
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#define AR8327_FWD_CTRL1_IGMP_S 24
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#define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
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#define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7)
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#define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2)
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#define AR8327_PORT_LOOKUP_IN_MODE_S 8
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#define AR8327_PORT_LOOKUP_STATE BITS(16, 3)
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#define AR8327_PORT_LOOKUP_STATE_S 16
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#define AR8327_PORT_LOOKUP_LEARN BIT(20)
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#define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
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#define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc)
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#define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
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#define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
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#define AR8337_PAD_MAC06_EXCHANGE_EN BIT(31)
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enum ar8327_led_pattern {
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AR8327_LED_PATTERN_OFF = 0,
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AR8327_LED_PATTERN_BLINK,
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AR8327_LED_PATTERN_ON,
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AR8327_LED_PATTERN_RULE,
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};
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struct ar8327_led_entry {
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unsigned reg;
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unsigned shift;
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};
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struct ar8327_led {
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struct led_classdev cdev;
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struct ar8xxx_priv *sw_priv;
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char *name;
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bool active_low;
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u8 led_num;
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enum ar8327_led_mode mode;
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struct mutex mutex;
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spinlock_t lock;
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struct work_struct led_work;
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bool enable_hw_mode;
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enum ar8327_led_pattern pattern;
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};
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struct ar8327_data {
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u32 port0_status;
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u32 port6_status;
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struct ar8327_led **leds;
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unsigned int num_leds;
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/* all fields below are cleared on reset */
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bool eee[AR8XXX_NUM_PHYS];
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};
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#endif
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