36 lines
1 KiB
Diff
36 lines
1 KiB
Diff
The code is rather based on trial-and-error than knowledge. Verified Via
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Rhine functionality in PIO as well as MMIO mode.
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Signed-off-by: Phil Sutter <n0-1@freewrt.org>
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Tested-by: Florian Fainelli <florian@openwrt.org>
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---
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arch/mips/pci/pci-rc32434.c | 11 +++++++++++
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1 files changed, 11 insertions(+), 0 deletions(-)
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--- a/arch/mips/pci/pci-rc32434.c
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+++ b/arch/mips/pci/pci-rc32434.c
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@@ -205,6 +205,8 @@ static int __init rc32434_pcibridge_init
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static int __init rc32434_pci_init(void)
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{
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+ void __iomem *io_map_base;
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+
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pr_info("PCI: Initializing PCI\n");
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ioport_resource.start = rc32434_res_pci_io1.start;
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@@ -212,6 +214,15 @@ static int __init rc32434_pci_init(void)
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rc32434_pcibridge_init();
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+ io_map_base = ioremap(rc32434_res_pci_io1.start,
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+ rc32434_res_pci_io1.end - rc32434_res_pci_io1.start + 1);
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+
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+ if (!io_map_base)
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+ return -ENOMEM;
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+
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+ rc32434_controller.io_map_base =
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+ (unsigned long)io_map_base - rc32434_res_pci_io1.start;
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+
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register_pci_controller(&rc32434_controller);
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rc32434_sync();
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