7903a9219c
A newer clk and cpufreq drivers for ipq806x platform had been sent upstream. A change that i have noticed is that now it's possible to set min, cur and max frequencies from sysfs (previously it was bugged and caused nothing). Following patches are removed: - 0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch - seems it was dropped from the patchset by current committer. - 0044-clk-qcom-krait-Remove-CLK_IS_ROOT.patch - already applied to the driver itself in the corresponding patch. - 0057-clk-qcom-Add-regmap-mux-div-clocks-support.patch - seem to be irrelevant to ipq806x. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
195 lines
5.9 KiB
Diff
195 lines
5.9 KiB
Diff
From patchwork Fri Dec 8 09:42:20 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v4,02/12] clk: mux: Split out register accessors for reuse
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From: Sricharan R <sricharan@codeaurora.org>
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X-Patchwork-Id: 10102103
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Message-Id: <1512726150-7204-3-git-send-email-sricharan@codeaurora.org>
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To: mturquette@baylibre.com, sboyd@codeaurora.org,
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devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
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linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
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viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
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Cc: sricharan@codeaurora.org
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Date: Fri, 8 Dec 2017 15:12:20 +0530
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From: Stephen Boyd <sboyd@codeaurora.org>
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We want to reuse the logic in clk-mux.c for other clock drivers
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that don't use readl as register accessors. Fortunately, there
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really isn't much to the mux code besides the table indirection
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and quirk flags if you assume any bit shifting and masking has
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been done already. Pull that logic out into reusable functions
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that operate on an optional table and some flags so that other
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drivers can use the same logic.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/clk-mux.c | 75 +++++++++++++++++++++++++++-----------------
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include/linux/clk-provider.h | 9 ++++--
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2 files changed, 54 insertions(+), 30 deletions(-)
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--- a/drivers/clk/clk-mux.c
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+++ b/drivers/clk/clk-mux.c
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@@ -26,35 +26,24 @@
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* parent - parent is adjustable through clk_set_parent
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*/
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-static u8 clk_mux_get_parent(struct clk_hw *hw)
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+unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
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+ unsigned int *table, unsigned long flags)
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{
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- struct clk_mux *mux = to_clk_mux(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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- u32 val;
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-
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- /*
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- * FIXME need a mux-specific flag to determine if val is bitwise or numeric
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- * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
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- * to 0x7 (index starts at one)
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- * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
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- * val = 0x4 really means "bit 2, index starts at bit 0"
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- */
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- val = clk_readl(mux->reg) >> mux->shift;
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- val &= mux->mask;
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- if (mux->table) {
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+ if (table) {
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int i;
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for (i = 0; i < num_parents; i++)
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- if (mux->table[i] == val)
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+ if (table[i] == val)
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return i;
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return -EINVAL;
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}
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- if (val && (mux->flags & CLK_MUX_INDEX_BIT))
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+ if (val && (flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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- if (val && (mux->flags & CLK_MUX_INDEX_ONE))
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+ if (val && (flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= num_parents)
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@@ -62,23 +51,53 @@ static u8 clk_mux_get_parent(struct clk_
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return val;
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}
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+EXPORT_SYMBOL_GPL(clk_mux_get_parent);
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-static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
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+static u8 _clk_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val;
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- unsigned long flags = 0;
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- if (mux->table) {
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- index = mux->table[index];
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+ /*
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+ * FIXME need a mux-specific flag to determine if val is bitwise or
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+ * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
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+ * but ranges from 0x1 to 0x7 (index starts at one)
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+ * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
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+ * val = 0x4 really means "bit 2, index starts at bit 0"
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+ */
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+ val = clk_readl(mux->reg) >> mux->shift;
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+ val &= mux->mask;
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+
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+ return clk_mux_get_parent(hw, val, mux->table, mux->flags);
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+}
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+
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+unsigned int clk_mux_reindex(u8 index, unsigned int *table,
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+ unsigned long flags)
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+{
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+ unsigned int val = index;
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+
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+ if (table) {
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+ val = table[val];
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} else {
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- if (mux->flags & CLK_MUX_INDEX_BIT)
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- index = 1 << index;
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+ if (flags & CLK_MUX_INDEX_BIT)
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+ val = 1 << index;
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- if (mux->flags & CLK_MUX_INDEX_ONE)
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- index++;
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+ if (flags & CLK_MUX_INDEX_ONE)
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+ val++;
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}
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+ return val;
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+}
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+EXPORT_SYMBOL_GPL(clk_mux_reindex);
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+
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+static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
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+{
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+ struct clk_mux *mux = to_clk_mux(hw);
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+ u32 val;
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+ unsigned long flags = 0;
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+
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+ index = clk_mux_reindex(index, mux->table, mux->flags);
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+
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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@@ -102,14 +121,14 @@ static int clk_mux_set_parent(struct clk
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}
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const struct clk_ops clk_mux_ops = {
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- .get_parent = clk_mux_get_parent,
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+ .get_parent = _clk_mux_get_parent,
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.set_parent = clk_mux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_mux_ops);
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const struct clk_ops clk_mux_ro_ops = {
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- .get_parent = clk_mux_get_parent,
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+ .get_parent = _clk_mux_get_parent,
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};
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EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
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@@ -117,7 +136,7 @@ struct clk_hw *clk_hw_register_mux_table
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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- u8 clk_mux_flags, u32 *table, spinlock_t *lock)
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+ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
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{
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struct clk_mux *mux;
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struct clk_hw *hw;
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--- a/include/linux/clk-provider.h
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+++ b/include/linux/clk-provider.h
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@@ -466,7 +466,7 @@ void clk_hw_unregister_divider(struct cl
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struct clk_mux {
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struct clk_hw hw;
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void __iomem *reg;
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- u32 *table;
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+ unsigned int *table;
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u32 mask;
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u8 shift;
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u8 flags;
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@@ -484,6 +484,11 @@ struct clk_mux {
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extern const struct clk_ops clk_mux_ops;
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extern const struct clk_ops clk_mux_ro_ops;
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+unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
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+ unsigned int *table, unsigned long flags);
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+unsigned int clk_mux_reindex(u8 index, unsigned int *table,
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+ unsigned long flags);
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+
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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@@ -504,7 +509,7 @@ struct clk_hw *clk_hw_register_mux_table
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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- u8 clk_mux_flags, u32 *table, spinlock_t *lock);
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+ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
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void clk_unregister_mux(struct clk *clk);
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void clk_hw_unregister_mux(struct clk_hw *hw);
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