3ddd2b49a9
This will allow ipq806x to support multiple kernel version more easily. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 44616
172 lines
4.1 KiB
Diff
172 lines
4.1 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -18,8 +18,15 @@
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bootargs = "console=ttyMSM0,115200 root=/dev/mtdblock12 rootfstype=squashfs,jffs2";
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};
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+ aliases {
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+ mdio-gpio0 = &mdio0;
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+ };
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+
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soc {
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pinmux@800000 {
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+ pinctrl-0 = <&mdio0_pins &rgmii2_pins>;
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+ pinctrl-names = "default";
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+
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i2c4_pins: i2c4_pinmux {
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pins = "gpio12", "gpio13";
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function = "gsbi4";
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@@ -34,6 +41,25 @@
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bias-none;
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};
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};
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+
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+ mdio0_pins: mdio0_pins {
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+ mux {
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+ pins = "gpio0", "gpio1";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+
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+ rgmii2_pins: rgmii2_pins {
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+ mux {
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+ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
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+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
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+ function = "rgmii2";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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};
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gsbi@16300000 {
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@@ -72,6 +98,7 @@
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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+ m25p,fast-read;
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partition@0 {
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label = "0:SBL1";
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@@ -148,5 +175,66 @@
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sata@29000000 {
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status = "ok";
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};
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+
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+ mdio0: mdio {
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+ compatible = "virtual,mdio-gpio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
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+
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+ phy0: ethernet-phy@0 {
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+ device_type = "ethernet-phy";
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+ reg = <0>;
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+ qca,ar8327-initvals = <
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+ 0x00004 0x7600000 /* PAD0_MODE */
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+ 0x00008 0x1000000 /* PAD5_MODE */
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+ 0x0000c 0x80 /* PAD6_MODE */
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+ 0x000e4 0xaa545 /* MAC_POWER_SEL */
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+ 0x000e0 0xc74164de /* SGMII_CTRL */
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+ 0x0007c 0x4e /* PORT0_STATUS */
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+ 0x00094 0x4e /* PORT6_STATUS */
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+ >;
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+ };
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+
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+ phy4: ethernet-phy@4 {
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+ device_type = "ethernet-phy";
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+ reg = <4>;
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+ };
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+ };
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+
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+ nss-gmac-common {
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+ reg = <0x03000000 0x0000FFFF 0x1bb00000 0x0000FFFF 0x00900000 0x00004000>;
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+ reg-names = "nss_reg_base" , "qsgmii_reg_base", "clk_ctl_base";
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+ };
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+
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+ gmac1: ethernet@37200000 {
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+ status = "ok";
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+ phy-mode = "rgmii";
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+ qcom,id = <1>;
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+ qcom,phy_mdio_addr = <4>;
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+ qcom,poll_required = <1>;
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+ qcom,rgmii_delay = <0>;
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+ qcom,emulation = <0>;
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+ qcom,forced_speed = <1000>;
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+ qcom,forced_duplex = <1>;
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+ qcom,socver = <0>;
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+ local-mac-address = [000000000000];
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+ mdiobus = <&mdio0>;
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+ };
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+
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+ gmac2: ethernet@37400000 {
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+ status = "ok";
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+ phy-mode = "sgmii";
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+ qcom,id = <2>;
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+ qcom,phy_mdio_addr = <0>;
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+ qcom,poll_required = <0>;
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+ qcom,rgmii_delay = <0>;
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+ qcom,emulation = <0>;
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+ qcom,forced_speed = <1000>;
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+ qcom,forced_duplex = <1>;
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+ qcom,socver = <0>;
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+ local-mac-address = [000000000000];
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+ mdiobus = <&mdio0>;
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -3,6 +3,7 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -279,5 +280,42 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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+
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+ nss-gmac-common {
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+ reg = <0x03000000 0x0000FFFF 0x1bb00000 0x0000FFFF 0x00900000 0x00004000>;
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+ reg-names = "nss_reg_base" , "qsgmii_reg_base", "clk_ctl_base";
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+ };
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+
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+ gmac0: ethernet@37000000 {
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+ device_type = "network";
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+ compatible = "qcom,nss-gmac";
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+ reg = <0x37000000 0x200000>;
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+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ gmac1: ethernet@37200000 {
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+ device_type = "network";
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+ compatible = "qcom,nss-gmac";
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+ reg = <0x37200000 0x200000>;
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+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ gmac2: ethernet@37400000 {
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+ device_type = "network";
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+ compatible = "qcom,nss-gmac";
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+ reg = <0x37400000 0x200000>;
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+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ gmac3: ethernet@37600000 {
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+ device_type = "network";
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+ compatible = "qcom,nss-gmac";
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+ reg = <0x37600000 0x200000>;
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+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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};
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};
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