3c1f6e358d
Patches are generated using the "format-patch" command from the following location: *https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base *rev=0771849495b4128cac2faf7d49c85c729fc48b20 Patches numbered 76/77/102/103 have already been integrated in 3.14.12, so they're not in this list. All these patches are either integrated are pending integration into kernel.org, therefore these patches should go away once the kernel gets upgraded to 3.16. Support is currently limited to AP148 board but can be extended to other platforms in the future. These changes do not cover ethernet connectivity. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 42334
216 lines
4.7 KiB
Diff
216 lines
4.7 KiB
Diff
From 8c52931421759b70fc37771be3390813a2a2f9f5 Mon Sep 17 00:00:00 2001
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From: Georgi Djakov <gdjakov@mm-sol.com>
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Date: Fri, 23 May 2014 18:12:29 +0300
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Subject: [PATCH 096/182] ARM: dts: qcom: Add APQ8084 SoC support
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Add support for the Qualcomm Snapdragon 805 APQ8084 SoC. It is
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used on APQ8084-MTP and other boards.
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Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-apq8084.dtsi | 179 +++++++++++++++++++++++++++++++++++
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arch/arm/mach-qcom/board.c | 1 +
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2 files changed, 180 insertions(+)
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create mode 100644 arch/arm/boot/dts/qcom-apq8084.dtsi
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diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
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new file mode 100644
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index 0000000..e3e009a
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
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@@ -0,0 +1,179 @@
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+/dts-v1/;
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+
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+#include "skeleton.dtsi"
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+
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+/ {
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+ model = "Qualcomm APQ 8084";
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+ compatible = "qcom,apq8084";
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+ interrupt-parent = <&intc>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <0>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc0>;
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+ };
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+
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+ cpu@1 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <1>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc1>;
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+ };
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+
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+ cpu@2 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <2>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc2>;
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+ };
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+
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+ cpu@3 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <3>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc3>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "qcom,arch-cache";
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+ cache-level = <2>;
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+ qcom,saw = <&saw_l2>;
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+ };
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+ };
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+
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+ cpu-pmu {
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+ compatible = "qcom,krait-pmu";
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+ interrupts = <1 7 0xf04>;
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+ };
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+
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+ timer {
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+ compatible = "arm,armv7-timer";
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+ interrupts = <1 2 0xf08>,
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+ <1 3 0xf08>,
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+ <1 4 0xf08>,
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+ <1 1 0xf08>;
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+ clock-frequency = <19200000>;
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+ };
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+
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+ soc: soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "simple-bus";
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+
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+ intc: interrupt-controller@f9000000 {
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+ compatible = "qcom,msm-qgic2";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = <0xf9000000 0x1000>,
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+ <0xf9002000 0x1000>;
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+ };
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+
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+ timer@f9020000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "arm,armv7-timer-mem";
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+ reg = <0xf9020000 0x1000>;
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+ clock-frequency = <19200000>;
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+
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+ frame@f9021000 {
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+ frame-number = <0>;
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+ interrupts = <0 8 0x4>,
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+ <0 7 0x4>;
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+ reg = <0xf9021000 0x1000>,
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+ <0xf9022000 0x1000>;
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+ };
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+
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+ frame@f9023000 {
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+ frame-number = <1>;
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+ interrupts = <0 9 0x4>;
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+ reg = <0xf9023000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9024000 {
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+ frame-number = <2>;
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+ interrupts = <0 10 0x4>;
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+ reg = <0xf9024000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9025000 {
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+ frame-number = <3>;
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+ interrupts = <0 11 0x4>;
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+ reg = <0xf9025000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9026000 {
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+ frame-number = <4>;
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+ interrupts = <0 12 0x4>;
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+ reg = <0xf9026000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9027000 {
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+ frame-number = <5>;
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+ interrupts = <0 13 0x4>;
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+ reg = <0xf9027000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9028000 {
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+ frame-number = <6>;
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+ interrupts = <0 14 0x4>;
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+ reg = <0xf9028000 0x1000>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ saw_l2: regulator@f9012000 {
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+ compatible = "qcom,saw2";
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+ reg = <0xf9012000 0x1000>;
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+ regulator;
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+ };
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+
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+ acc0: clock-controller@f9088000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf9088000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ acc1: clock-controller@f9098000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf9098000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ acc2: clock-controller@f90a8000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf90a8000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ acc3: clock-controller@f90b8000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf90b8000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ restart@fc4ab000 {
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+ compatible = "qcom,pshold";
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+ reg = <0xfc4ab000 0x4>;
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+ };
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+ };
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+};
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diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
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index 350fa8d..c437a99 100644
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--- a/arch/arm/mach-qcom/board.c
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+++ b/arch/arm/mach-qcom/board.c
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@@ -17,6 +17,7 @@
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static const char * const qcom_dt_match[] __initconst = {
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"qcom,apq8064",
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"qcom,apq8074-dragonboard",
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+ "qcom,apq8084",
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"qcom,msm8660-surf",
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"qcom,msm8960-cdp",
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NULL
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--
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1.7.10.4
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