107 lines
2.8 KiB
Diff
107 lines
2.8 KiB
Diff
From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
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From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
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Date: Tue, 17 Nov 2015 17:18:41 +0800
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Subject: [PATCH 20/81] arm64: dts: mediatek: add xHCI & usb phy for mt8173
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add xHCI and phy drivers for MT8173-EVB
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Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 16 ++++++++++
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arch/arm64/boot/dts/mediatek/mt8173.dtsi | 42 +++++++++++++++++++++++++++
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2 files changed, 58 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
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@@ -13,6 +13,7 @@
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*/
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/dts-v1/;
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+#include <dt-bindings/gpio/gpio.h>
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#include "mt8173.dtsi"
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/ {
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@@ -32,6 +33,15 @@
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};
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chosen { };
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+
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+ usb_p1_vbus: regulator@0 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
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+ enable-active-high;
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+ };
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};
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&i2c1 {
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@@ -408,3 +418,9 @@
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&uart0 {
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status = "okay";
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};
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+
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+&usb30 {
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+ vusb33-supply = <&mt6397_vusb_reg>;
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+ vbus-supply = <&usb_p1_vbus>;
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+ mediatek,wakeup-src = <1>;
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+};
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--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
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@@ -14,6 +14,7 @@
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mt8173-power.h>
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#include <dt-bindings/reset-controller/mt8173-resets.h>
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#include "mt8173-pinfunc.h"
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@@ -510,6 +511,47 @@
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status = "disabled";
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};
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+ usb30: usb@11270000 {
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+ compatible = "mediatek,mt8173-xhci";
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+ reg = <0 0x11270000 0 0x1000>,
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+ <0 0x11280700 0 0x0100>;
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+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
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+ clocks = <&topckgen CLK_TOP_USB30_SEL>,
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+ <&pericfg CLK_PERI_USB0>,
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+ <&pericfg CLK_PERI_USB1>;
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+ clock-names = "sys_ck",
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+ "wakeup_deb_p0",
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+ "wakeup_deb_p1";
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+ phys = <&phy_port0 PHY_TYPE_USB3>,
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+ <&phy_port1 PHY_TYPE_USB2>;
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+ mediatek,syscon-wakeup = <&pericfg>;
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+ status = "okay";
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+ };
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+
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+ u3phy: usb-phy@11290000 {
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+ compatible = "mediatek,mt8173-u3phy";
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+ reg = <0 0x11290000 0 0x800>;
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+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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+ clock-names = "u3phya_ref";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "okay";
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+
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+ phy_port0: port@11290800 {
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+ reg = <0 0x11290800 0 0x800>;
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+
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+ phy_port1: port@11291000 {
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+ reg = <0 0x11291000 0 0x800>;
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+ };
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+
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mmsys: clock-controller@14000000 {
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compatible = "mediatek,mt8173-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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