ff08b09570
All (still relevant) patches were refresh. The following patches were dropped because they are applied upstream: - 0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch - 0005-MIPS-lantiq-add-reset-controller-api-support.patch - 0006-MIPS-lantiq-reboot-gphy-on-restart.patch - 0009-MIPS-lantiq-command-line-work-around.patch - 0010-MIPS-lantiq-export-soc-type.patch - 0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch - 0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 46216
44 lines
1.4 KiB
Diff
44 lines
1.4 KiB
Diff
From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 28 Jul 2013 18:06:39 +0200
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Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be
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persistent
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/nand/xway_nand.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/mtd/nand/xway_nand.c
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+++ b/drivers/mtd/nand/xway_nand.c
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@@ -54,6 +54,8 @@
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#define NAND_CON_CSMUX (1 << 1)
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#define NAND_CON_NANDM 1
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+static u32 xway_latchcmd;
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+
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static void xway_reset_chip(struct nand_chip *chip)
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{
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unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
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@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf
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unsigned long flags;
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if (ctrl & NAND_CTRL_CHANGE) {
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- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
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if (ctrl & NAND_CLE)
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- nandaddr |= NAND_WRITE_CMD;
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- else
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- nandaddr |= NAND_WRITE_ADDR;
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- this->IO_ADDR_W = (void __iomem *) nandaddr;
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+ xway_latchcmd = NAND_WRITE_CMD;
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+ else if (ctrl & NAND_ALE)
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+ xway_latchcmd = NAND_WRITE_ADDR;
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}
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if (cmd != NAND_CMD_NONE) {
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spin_lock_irqsave(&ebu_lock, flags);
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- writeb(cmd, this->IO_ADDR_W);
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+ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
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while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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;
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spin_unlock_irqrestore(&ebu_lock, flags);
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