c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
43 lines
1.6 KiB
Diff
43 lines
1.6 KiB
Diff
From 7f434723cdb6823443330cd4847d5c3b8dd30bd7 Mon Sep 17 00:00:00 2001
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From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
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Date: Fri, 18 Dec 2015 14:38:55 +0200
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Subject: [PATCH 51/70] PCI: designware: Ensure ATU is enabled before IO/conf
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space accesses
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Read back the ATU CR2 register to ensure ATU programming is effective
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before any subsequent I/O or config space accesses.
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Without this, PCI device enumeration is unreliable.
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[bhelgaas: changelog, comment]
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Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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---
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drivers/pci/host/pcie-designware.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pc
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static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
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int type, u64 cpu_addr, u64 pci_addr, u32 size)
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{
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+ u32 val;
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+
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dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
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@@ -164,6 +166,12 @@ static void dw_pcie_prog_outbound_atu(st
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dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
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dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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+
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+ /*
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+ * Make sure ATU enable takes effect before any subsequent config
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+ * and I/O accesses.
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+ */
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+ dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
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}
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static struct irq_chip dw_msi_irq_chip = {
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